ZL30121GGG ZARLINK [Zarlink Semiconductor Inc], ZL30121GGG Datasheet
ZL30121GGG
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ZL30121GGG Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved. Low Jitter System Synchronizer an email to ZL30121GGG ZL30121GGG2 100 Pin CABGA* *Pb Free Tin/Silver/Copper • Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz • ...
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Applications TM • AdvancedTCA Systems • Multi-Service Edge Switches or Routers • Multi-Service Provisioning Platforms (MSPPs) • Add-Drop Multiplexers (ADMs) • Wireless/Wireline Gateways • Wireless Base Stations • DSLAM / Next Gen DLC • Core Routers ZL30121 2 Zarlink Semiconductor ...
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Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - DPLL1 and DPLL2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pin Description I/O Pin # Name Type Input Reference C1 ref0 I Input References (LVCMOS, Schmitt Trigger). These are input references d B2 ref1 available to both DPLL1 and DPLL2 for synchronizing output clocks. All eight A3 ref2 input references ...
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I/O Pin # Name Type K8 p0_fp0 O Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse associated with the p0 clocks. The default frequency for ...
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I/O Pin # Name Type K1 diff0_en I Differential Output 0 Enable (LVCMOS, Schmitt Trigger). When set high, the u differential LVPECL output 0 driver is enabled. When set low, the differential driver is tristated reducing power consumption. This pin ...
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I/O Pin # Name Type J3 tms I Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of u the TAP controller. This pin is internally pulled then it should be left unconnected. Master Clock ...
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I/O Pin # Name Type Ground. 0 Volts ...
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Functional Description The ZL30121 SONET/SDH System Synchronizer is a highly integrated device that provides the functionality required for synchronizing network equipment. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a ...
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Feature Supported Output As listed in Table 4 Frame Pulse Frequencies External Status Pin Lock, Holdover Indicators 1. Limited for 2 kHz references the wideband mode, the loop bandwidth depends on the frequency of the ...
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Normal (locked) The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency ...
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In addition to the reference inputs, DPLL1 has three optional frame pulse synchronization inputs (sync0 to sync2) used to align the output frame pulses. The sync or 2. Note that the sync input cannot be used to synchronize the DPLL, ...
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Ref and Sync Monitoring All input references (ref0 to ref7) are monitored for frequency accuracy and phase regularity. New references are qualified before they can be selected as a synchronization source and qualified references are continuously monitored to ensure ...
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All sync inputs (sync0 to sync2) are continuously monitored to ensure that there is a correct number of reference clock cycles within the frame pulse period. 1.5 Output Clocks and Frame Pulses The ZL30121 offers a wide variety of outputs ...
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The supported frequencies for the output clocks and frame pulses are shown in Table 4. diff0_p/n, sdh_clk0, diff1_p/n sdh_clk1 (LVPECL) (LVCMOS) 6.48 MHz 6.48 MHz 19.44 MHz 9.72 MHz 38.88 MHz 12.96 MHz 51.84 MHz 19.44 MHz 77.76 MHz 25.92 ...
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Configurable Input-to-Output and Output-to-Output Delays The ZL30121 allows programmable static delay compensation for controlling input-to-output and output-to-output delays of its clocks and frame pulses. All of the output synthesizers (SONET/SDH, P0, P1, Feedback) locked to DPLL1 can be configured ...
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Master/Slave Configuration In systems that provide redundant timing sources desirable to minimize the output skew between the master and the slave’s output clocks. This can be achieved by synchronizing the slave to one of the master’s output ...
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External Feedback Inputs In addition to the static delay compensation described in the “External Feedback Inputs” section on page 20, the ZL30121 also provides the option of dynamic delay compensation to minimize path delay variation associated with external clock ...
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Software Configuration The ZL30121 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The device can be configured to operate in a highly automated manner which minimizes its interaction with the system’s processor ...
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Addr Register (Hex) Name 0F ref_mon_fail_mask_3 10 detected_ref_0 11 detected_ref_1 12 detected_ref_2 13 detected_ref_3 14 detected_sync_0 15 detected_sync_1 16 oor_ctrl_0 17 oor_ctrl_1 18 oor_ctrl_2 19 oor_ctrl_3 1A gst_mask_0 1B gst_mask_1 1C gst_qualif_time 1D dpll1_ctrl_0 1E dpll1_ctrl_1 ZL30121 Reset Value Description ...
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Addr Register (Hex) Name 1F dpll1_modesel 20 dpll1_refsel 21 dpll1_ref_fail_mask 22 dpll1_wait_to_restore 23 dpll1_ref_rev_ctrl 24 dpll1_ref_pri_ctrl_0 25 dpll1_ref_pri_ctrl_1 26 dpll1_ref_pri_ctrl_2 27 dpll1_ref_pri_ctrl_3 28 dpll1_lock_holdover_status 29 dpll1_pullinrange 2A dpll2_ctrl_0 2B dpll2_ctrl_1 2C dpll2_modesel 2D dpll2_refsel 2E dpll2_ref_fail_mask 2F dpll2_wait_to_restore 30 dpll2_ref_rev_ctrl ...
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Addr Register (Hex) Name 31 dpll2_ref_pri_ctrl_0 32 dpll2_ref_pri_ctrl_1 33 dpll2_ref_pri_ctrl_2 34 dpll2_ref_pri_ctrl_3 35 dpll2_lock_holdover_status 36 p0_enable 37 p0_run 38 p0_freq_0 39 p0_freq_1 3A p0_clk0_offset90 3B p0_clk1_div 3C p0_clk1_offset90 3D p0_offset_fine 3E p0_fp0_freq 3F p0_fp0_type 40 p0_fp0_fine_offset_0 41 p0_fp0_fine_offset_1 42 p0_fp0_coarse_offset ...
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Addr Register (Hex) Name 44 p0_fp1_type 45 p0_fp1_fine_offset_0 46 p0_fp1_fine_offset_1 47 p0_fp1_coarse_offset 48 p1_enable 49 p1_run 4A p1_freq_0 4B p1_freq_1 4C p1_clk0_offset90 4D p1_clk1_div 4E p1_clk1_offset90 4F p1_offset_fine 50 sdh_enable 51 sdh_run 52 sdh_clk_div 53 sdh_clk0_offset90 54 sdh_clk1_offset90 55 sdh_offset_fine ...
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Addr Register (Hex) Name 56 sdh_fp0_freq 57 sdh_fp0_type 58 sdh_fp0_fine_offset_0 59 sdh_fp0_fine_offset_1 5A sdh_fp0_coarse_offset 5B sdh_fp1_freq 5C sdh_fp1_type 5D sdh_fp1_fine_offset_0 5E sdh_fp1_fine_offset_1 5F sdh_fp1_coarse_offset 60 diff_ctrl 61 diff_sel 62 fb_control 63 fb_offset_fine 64 reserved 65 ref_freq_mode_0 66 ref_freq_mode_1 67 custA_mult_0 ...
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Addr Register (Hex) Name 68 custA_mult_1 69 custA_scm_low 6A custA_scm_high 6B custA_cfm_low_0 6C custA_cfm_low_1 6D custA_cfm_hi_0 6E custA_cfm_hi_1 6F custA_cfm_cycle 70 custA_div 71 custB_mult_0 72 custB_mult_1 73 custB_scm_low 74 custB_scm_high 75 custB_cfm_low_0 76 custB_cfm_low_1 ZL30121 Reset Value Description (Hex) 00 ...
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Addr Register (Hex) Name 77 custB_cfm_hi_0 78 custB_cfm_hi_1 79 custB_cfm_cycle 7A custB_div 7B - Reserved 7F 3.0 References AdvancedTCA, ATCA and the AdvancedTCA and ATCA logos are trademarks of the PCI Industrial Computer Manufacturers Group. ZL30121 Reset Value Description (Hex) ...
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