ZL30121GGG ZARLINK [Zarlink Semiconductor Inc], ZL30121GGG Datasheet - Page 9

• Manufacturer Part Number: ZL30121GGG
• Description: SONET/SDH Low Jitter System Synchronizer
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Master Clock
Miscellaneous
Power and Ground
Pin #
C10
G3
G8
G9
K4
K5
H7
K6
D9
E4
H6
H8
E8
A5
A8
B7
B8
H2
F2
F3
F4
J2
J6
J8
J9
J3
AV
V
Name
AV
osco
V
osci
tms
CORE
NC
IC
IC
CORE
DD
DD
Type
I/O
I
O
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
I
u
Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of
the TAP controller. This pin is internally pulled up to V
then it should be left unconnected.
Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz
reference from a clock oscillator (TCXO, OCXO). The stability and accuracy of
the clock at this input determines the free-run accuracy and the long term
holdover stability of the output clocks.
Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected
when the osci pin is connected to a clock oscillator.
Internal Connection. Connect to ground.
Internal Connection. Leave unconnected.
No Connection. Leave unconnected.
Positive Supply Voltage. +3.3V
Positive Supply Voltage. +1.8V
Positive Analog Supply Voltage. +3.3V
Positive Analog Supply Voltage. +1.8V
Zarlink Semiconductor Inc.
ZL30121
9
DC
DC
Description
nominal.
nominal.
DC
DC
nominal.
nominal.
DD
. If this pin is not used
Data Sheet