ZL30406QGC ZARLINK [Zarlink Semiconductor Inc], ZL30406QGC Datasheet
ZL30406QGC
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ZL30406QGC Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. SONET/SDH Clock Multiplier PLL Ordering Information ZL30406QGC ZL30406QGC1 Description The ZL30406 is an analog phase-locked loop (APLL) designed to provide rate conversion and jitter attenuation for SDH (Synchronous Digital Hierarchy) ...
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GND VCC1 VCC OC-CLKoN OC-CLKoP GND VCC2 LPF GND GND BIAS OC-CLKoEN C77oEN-A C77oEN-B C77oEN-C C77oEN-D Pin Description Pin Description Table Pin # Name 1 GND 2 VCC1 3 VCC 4 OC-CLKoN 5 OC-CLKoP 6 GND 7 VCC2 LPF 8 ...
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Pin Description Table (continued) Pin # Name 12 OC-CLKoEN C77oEN-A 13 C77oEN-B 14 C77oEN-C 15 C77oEN GND 18 VDD VDD FS2 25 FS1 26 C19oEN 27 GND 28 ...
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Pin Description Table (continued) Pin # Name 36 GND GND 39 GND GND 42 VDD 43 GND 44 VCC 45 GND 46 VDD 47 VCC 48 GND 49 VCC 50 C77oN-D 51 C77oP-D 52 ...
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Functional Description The ZL30406 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30406 is shown in Figure 1 and a brief description ...
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Output Interface Circuit The output of the VCO is used by the Output Interface Circuit to provide four LVPECL differential clocks at 77.76 MHz, one programmable CML differential clock (19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz) controlled with ...
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Applications 2.1 Ultra-Low Jitter SONET/SDH Equipment Clocks The ZL30406 functionality and performance complements the entire family of the Zarlink’s advanced network synchronization PLLs. Its superior jitter filtering characteristics exceed requirements of SONET/SDH optical interfaces operating at OC-48/STM-16 rate (2.5 ...
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The ZL30406 in combination with the MT9046 provides an optimum solution for SONET/SDH line cards (see Figure 5). C19i = 680 Ω 820 PRI SEC Synchronization Reference RSEL Clocks ...
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Recommended Interface circuit 2.2.1 LVPECL to LVPECL Interface The C77oP/N-A, C77oP/N-B, C77oP/N-B, and C77oP/N-D outputs provide differential LVPECL clocks at 77.76 MHz. The LVPECL output drivers require a 50 Ω termination connected to the VCC-2V source for each output ...
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CML to LVDS Interface To configure the driver as an LVDS driver, external biasing resistors are required to set up the common mode voltage as specified by ANSI/TIA/EIA-644 LVDS standard. The standard specifies the V as minimum 1.125 V, ...
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Tristating LVPECL Outputs The ZL30406 has four differential 77.76 MHz LVPECL outputs, which can be used to drive four different OC-3/OC- 12/OC-48 devices such as framers, mappers and SERDES. In the case where fewer than four clocks are required, ...
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Power Supply and BIAS Circuit Filtering Recommendations Figure 11 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter performance. The level of required filtering is subject to further optimization and simplification. Please check Zarlink’s web ...
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Characteristics † Absolute Maximum Ratings Characteristics 1 Supply voltage 2 Voltage on any pin 3 Current on any pin 4 ESD Rating 5 Storage temperature 6 Package power dissipation † Voltages are with respect to ground unless otherwise stated. ...
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DC Electrical Characteristics (continued) Characteristics 7 CMOS: Input bias current for pulled-down inputs: FS1, FS2, C77oEN-A, C77oEN-C, C77oEN-D, OC-CLKoEN 8 CMOS: Input bias current for pulled-up inputs: , C77oEN-B, C19o_EN 9 CMOS: High-level output voltage 10 CMOS: Low-level output ...
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AC Electrical Characteristics - Output Timing Parameters Measurement Voltage Levels Characteristics 1 Threshold Voltage 2 Rise and Fall Threshold Voltage High 3 Rise and Fall Threshold Voltage Low All Signals Figure 12 - Output ...
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AC Electrical Characteristics - C19i Input to OC-CLKo Output Delay Timing (CML) Characteristics 1 C19i to OC-CLKo(19) delay 2 C19i to OC-CLKo(38) delay 3 C19i to OC-CLKo(77) delay 4 C19i to OC-CLKo(155) delay † Supply voltage and operating temperature ...
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AC Electrical Characteristics - C77 Clocks Output Timing Characteristics 1 C77oA to C77oB 2 C77oA to C77oC 3 C77oA to C77oD † Supply voltage and operating temperature are as per Recommended Operating Conditions. ‡ Typical figures are for design ...
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Performance Characteristics - Functional- Characteristics 1 Pull-in range 2 Lock Time Performance Characteristics: Output Jitter Generation - GR-253-CORE conformance - 40 to 85°C) GR-253-CORE Jitter Generation Requirements Interface Jitter (Category Measurement II) Filter 1 OC-48 STS-48 12 kHz - 20 ...
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Performance Characteristics: Output Jitter Generation - G.813 conformance (Option 1 and 2) ±10 -40 to 85°C) A G.813 Jitter Generation Requirements Jitter Interface Measurement Filter Option 1 1 STM-16 1 MHz to 20 MHz 5 kHz to 20 ...
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Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...