ZL30406QGC ZARLINK [Zarlink Semiconductor Inc], ZL30406QGC Datasheet - Page 10

• Manufacturer Part Number: ZL30406QGC
• Description: SONET/SDH Clock Multiplier PLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.2.3
To configure the driver as an LVDS driver, external biasing resistors are required to set up the common mode
voltage as specified by ANSI/TIA/EIA-644 LVDS standard. The standard specifies the V
as minimum 1.125 V, typical 1.2 V, and maximum 1.375 V. The following figure provides a recommendation for
LVDS applications.
2.2.4
In the case when more than four 77.76 MHz clocks are required to drive LVPECL receivers then the unused OC-
CLKo clock (CML output) can be configured to output the 77.76 MHz clock and interface to the LVPECL receiver as
is shown in the Figure 9. The terminating resistors should be placed as close as possible to the LVPECL receiver.
CML to LVDS Interface
CML to LVPECL Interface
ZL30406
Driver
Driver
GND
CML
CML
VCC
GND
VCC
OC-CLKoP
OC-CLKoN
OC-CLKoP
OC-CLKoN
ZL30406
Figure 9 - CML to LVPECL Interface
77.76MHz
Figure 8 - LVDS Termination
Typical resistor values: R1 = 82 Ω, R2 =130 Ω
Typical resistor values: R1 = 16 kΩ, R2 = 10 kΩ
Zarlink Semiconductor Inc.
ZL30406
+3.3 V
Z=50 Ω
Z=50 Ω
+3.3 V
Z=50 Ω
Z=50 Ω
10
0.1 uF
0.1 uF
10 nF
10 nF
10 nF
10 nF
VCC=+3.3 V
R1
R2
VCC=+3.3 V
R1
R2
R1
CM
R2
(common mode voltage)
R1
R2
LVDS
Receiver
100Ω
LVPECL
Receiver
Data Sheet