ZL30409/DDA ZARLINK [Zarlink Semiconductor Inc], ZL30409/DDA Datasheet
ZL30409/DDA
Related parts for ZL30409/DDA
ZL30409/DDA Summary of contents
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... Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912, France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. T1/E1 System Synchronizer ZL30409/DDA ZL30409/DDB Applications • Synchronization and timing control for multitrunk T1,E1 and STS-3/OC3 systems • ...
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The ZL30409 is compliant with Telcordia GR-1244-CORE Stratum 4 and ETSI ETS 300 011 2048 kbit/s interfaces. It will meet the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, holdover frequency and MTIE requirements for these specifications. ZL30409 ...
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Pin Description Pin # Name 1,10, GND Ground. 0 Volts. 23,31 2 RST Reset (Input). A logic low at this input resets the ZL30409. To ensure proper operation, the device must be reset after reference signal frequency changes and power-up. ...
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Pin Description (continued) Pin # Name 18 LOCK Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to the input reference. 19 C2o Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at ...
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Pin Description (continued) Pin # Name 45 TDI Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled TRST Test Reset (Input). Asynchronously initializes ...
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Programmable Delay Circuit PRI or SEC from Reference Select Mux As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the signal through a programmable delay line, and uses this ...
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Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase difference between the two. This ...
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The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal 50% duty cycle. From DPLL Figure 5 - Output Interface Circuit Block Diagram The T1 and E1 signals are generated ...
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All state machine changes occur synchronously on the rising edge of F8o. See the Control and Mode of Operation section for full details. RSEL Figure 6 - Control State Machine Block Diagram Master Clock The ZL30409 can use either a ...
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From a reset condition, the ZL30409 will take seconds (see AC Electrical Characteristics) of input reference signal to output signals which are synchronized (phase locked) to the reference input. The selection of input references is control dependent ...
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ZL30409 Measures of Performance The following are some synchronizer performance indicators and their corresponding definitions. Intrinsic Jitter Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output measured by applying a reference ...
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Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the ...
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Maximum Time Interval Error (MTIE) MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. MTIE Phase Continuity Phase continuity is the phase difference ...
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Description Input Controls MS2 MS1 RSEL PCCi Legend Change / Not Valid MTIE State ...
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Applications This section contains ZL30409 application specific details for clock and crystal operation, reset operation, power supply decoupling, and control operation. Master Clock The ZL30409 can use either a clock or crystal as the master timing source. In Freerun Mode, ...
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The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. Typically, for a 20MHz crystal specified with a 32pF load capacitance, each 1pF change ...
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ZL30409 from Holdover Mode to Normal Mode (with or without TIE Corrector Circuit) When 10 Normal to Holdover to Normal mode change sequences occur without MTIE enabled, and in each case ...
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Lock Indicator The LOCK pin toggles at a random rate when the PLL is frequency locked to the input reference. In Figure 11 the RC-time-constant circuit can be used to hold the high state of the LOCK pin. Once the ...
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ZL30409 Figure 12 - Digital Lock Pin Circuit ZL30409 19 Zarlink Semiconductor Inc. Data Sheet ...
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Absolute Maximum Ratings* - Parameter 1 Supply voltage 2 Voltage on any pin 3 Current on any pin 4 Storage temperature 5 48 SSOP package power dissipation * Exceeding these values may cause permanent damage. Functional operation under these conditions ...
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AC Electrical Characteristics - Performance Characteristics 1 Freerun Mode accuracy with OSCi at Holdover Mode accuracy with OSCi at Capture range with OSCi at Phase lock time 11 Output phase continuity ...
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AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels* - with respect to ground (GND) unless otherwise stated Characteristics 1 Threshold Voltage 2 Rise and Fall Threshold Voltage High 3 Rise and Fall Threshold Voltage Low * Supply voltage and ...
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AC Electrical Characteristics - Input/Output Timing Characteristics 1 Reference input pulse width high or low 2 Reference input rise or fall time 3 8kHz reference input to F8o delay 4 1.544MHz reference input to F8o delay 5 2.048MHz reference input ...
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PRI/SEC 8kHz PRI/SEC 1.544MHz PRI/SEC 2.048MHz PRI/SEC 19.44MHz F8o NOTES: 1. Input to output delay values are valid after a TCLR or RST with no further state changes Figure 14 - Input to Output Timing (Normal Mode) ZL30409 t RW ...
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F8o F0o F16o t C16o t t C8W C8W C8o t C4W C4o C2o t C6W C6o C1.5o C19o F8o C2o RSP TSP ZL30409 t FOWL t F16WL t F16S C16WL t C4W t C2W t C6W t C15W t ...
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F8o MS1,2, RSEL, PCCi Figure 17 - Input Controls Setup and Hold Timing AC Electrical Characteristics - Intrinsic Jitter Unfiltered Characteristics 1 Intrinsic jitter at F8o (8kHz) 2 Intrinsic jitter at F0o (8kHz) 3 Intrinsic jitter at F16o (8kHz) 4 ...
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AC Electrical Characteristics - 8kHz Input to 8kHz Output Jitter Transfer Characteristics 1 Jitter attenuation for 1Hz@0.01UIpp input 2 Jitter attenuation for 1Hz@0.54UIpp input 3 Jitter attenuation for 10Hz@0.10UIpp input 4 Jitter attenuation for 60Hz@0.10UIpp input 5 Jitter attenuation for ...
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AC Electrical Characteristics - 2.048MHz Input to 2.048MHz Output Jitter Transfer Characteristics 1 Jitter at output for 1Hz@3.00UIpp input with 40Hz to 100kHz filter 2 3 Jitter at output for 3Hz@2.33UIpp input with 40Hz to 100kHz filter 4 5 Jitter ...
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AC Electrical Characteristics - 8kHz Input Jitter Tolerance Characteristics 1 Jitter tolerance for 1Hz input 2 Jitter tolerance for 5Hz input 3 Jitter tolerance for 20Hz input 4 Jitter tolerance for 300Hz input 5 Jitter tolerance for 400Hz input 6 ...
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AC Electrical Characteristics - OSCi 20MHz Master Clock Input Characteristics 1 Tolerance Duty cycle 5 Rise time 6 Fall time † See "Notes" following AC Electrical Characteristics tables. † Notes: Voltages are with respect to ground (GND) ...
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Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...