MT90732AP MITEL [Mitel Networks Corporation], MT90732AP Datasheet

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MT90732AP

Manufacturer Part Number
MT90732AP
Description
CMOS E2/E3 Framer (E2/E3F)
Manufacturer
MITEL [Mitel Networks Corporation]
Datasheet
Features
Applications
U.S. Patent Number 5040170
Line Side
Framer for CCITT Recommendations
Line side interface
Transmit reference generator for bit-serial I/O
Microprocessor or control leads
I/O port for service bits
Line terminals
Wideband data or video transport
Test equipment
Multiplexer systems
HDB3 codec for dual rail I/O
Terminal side interface
RCK/RCKL
TCK/TCKL
FORCEFE
NRZ LINE
RP/RDL
TLCINV
TP/TDL
MICRO
RESET
BIP-4E
RLOC
RLOF
TLOC
TLBK
PLBK
BIP-4
RAIS
DAIS
ROD
ROC
TAIS
ROF
TOD
TOC
SER
TOF
LPT
RN
CV
M0
M1
FE
TN
- Bit-serial
- Nibble-parallel
- G.742 (8448 kbit/s)
- G.745 (8448 kbit/s)
- G.751 (34368 kbit/s)
- G.753 (34368 kbit/s)
- Dual rail or NRZ
TCKL
TDL
RDL
RCKL
Control
Decoder
Encoder
Line
Line
Clock
Data
Clock
Data
Figure 1 - Functional Block Diagram
Framer
G.7XX
Send
Frame
Clock
Data
Framing
Clock
Data
Description
The MT90732 E2/E3 Framer (E2/E3F) is a CMOS
VLSI device that provides the functions needed to
frame a wideband payload to one of four CCITT
Recommendations. G.742, G.745, G.751, or G.753.
The E2/E3 Framer interfaces to line circuitry with
either dual rail or NRZ signals. On the terminal side,
the interface can be either nibble-parallel or bit-
serial.
The MT90732 can be operated with or without a
microprocessor.
microprocessor, the E2/E3 Framer provides an 8-
byte memory map for control, performance counters
and alarm status. The MT90732 provides a transmit
and
overhead
recommendations. The overhead bits can also be
accessed by the microprocessor via the memory
map.
Interpreter
receive
Frame
Clock
MT90732AP
Data
bits
interface
Ordering Information
Reference
processor
Generator
Transmit
-40°C to +85°C
Output
Micro-
Input
When
CMOS
from
I/O
E2/E3 Framer (E2/E3F)
ISSUE 1
Advance Information
port
each
interfaced
68 Pin PLCC
SERIAL
RSD
TDOUT
TCG
TFOUT
RSC
RSF
RCG
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
SEL
ALE
RD
WR
RDY
XSF
N.C.
TCIN
XSD
XCK
N.C.
TCOUT
for
Terminal Side
MT90732
of
accessing
PARALLEL
the
RNIB3
RNIB2
RNIB1
RNIB0
RNC
RNF
N.C.
XNIB3
XNIB2
XNIB1
XNIB0
XCK
XNF
XNC
with
May 1995
four
5-15
the
a

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MT90732AP Summary of contents

Page 1

... TCK/TCKL Line Clock Encoder TN Line Side U.S. Patent Number 5040170 MT90732AP Description The MT90732 E2/E3 Framer (E2/E3F CMOS VLSI device that provides the functions needed to frame a wideband payload to one of four CCITT Recommendations. G.742, G.745, G.751, or G.753. The E2/E3 Framer interfaces to line circuitry with either dual rail or NRZ signals ...

Page 2

MT90732 CMOS 10 ROC ROF NRZLINE 14 BIP VDD 17 GND 18 19 MICRO SER 20 TLBK 21 22 PLBK TAIS 23 LPT 24 TLOC 25 26 FORCEFE Pin Description Power Supply ...

Page 3

Advance Information Line Side Transmit Pin # Name I/O/P 31 TP/TDL O 32 TCK/TCKL Note Input Output Power Terminal Interface Pin # Name I/O/P 61 RCG O 62 RNF/RSF O ...

Page 4

MT90732 CMOS Terminal Interface Pin # Name I/O/P 56 XNIB0/XSD I 57 XCK I 58 XNF O 59 XNC/TCOU O T Note Input Output Power Service Bit Interface Pin # Name I/O/P 9 ROD ...

Page 5

Advance Information Microprocessor Interface Pin # Name I/O RDY O Note Input Output Power Control Interface Pin # Name I/O/P 13 NRZLINE I 14 BIP ...

Page 6

MT90732 CMOS Control Interface Pin # Name I/O/P 30 RESET I 49 DAIS I 50 TLCINV RAIS O 7 RLOC O 8 RLOF TLOC O 60 BIP-4E O Note: I ...

Page 7

Advance Information The transmitter operates independently of the receiver, unless the loop timing feature(LPT) is selected, when the receive clock becomes the transmitted clock. In the transmit direction, the terminal side bit-serial interface consists of: data input signal (XSD), a ...

Page 8

MT90732 CMOS Notes. 5-22 Advance Information ...

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