ZL30462MCF ZARLINK [Zarlink Semiconductor Inc], ZL30462MCF Datasheet
ZL30462MCF
Related parts for ZL30462MCF
ZL30462MCF Summary of contents
Page 1
This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ ...
Page 2
... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. ZL30462MCF 40 SMTDIL Description The ZL30462 is a Timing Module, which functions as a complete system clock solution for general timing applications ...
Page 3
Pin Description Table Pin Number Name 1 C16o Clock 16.384 MHz (CMOS Output). This general purpose output may be used for ST-BUS operation with a 16.384 MHz clock. 2 C8o Clock 8.192 MHz (CMOS Output). This general purpose output may ...
Page 4
Pin Description Table (continued) Pin Number Name 16 JA155N-1 JA 155-1 Clock (LVPECL Output). This differential output provides a low jitter 17 JA155P-1 155.52 MHz clock. 18 AGND2 Ground Positive Power Supply.3.3 V DD3 20 AGND1 Ground. 21 ...
Page 5
Pin Description Table (continued) Pin Number Name 40 V Positive Power Supply. 3 1.0 Functional Description The ZL30462 offers a complete timing solution in a 1.2” x 1” module package. The module comprises three main components, a DPLL ...
Page 6
In Free-run Mode, the Core PLL locks to the 20 MHz Master Clock Oscillator (OSC). The stability of the generated clock remains the same as the stability of the Master Clock Oscillator. • In Normal Mode, the Core PLL ...
Page 7
Clock Synthesizer The output of the DCO is connected to the Clock Synthesizer that generates the output clocks and frame pulse. • C2o: 2.048 MHz clock with nominal 50% duty cycle • C8o: 8.192 MHz clock with nominal 50% ...
Page 8
Output Driver LVPECL Driver Note : Vcc = +3.3V Figure 3 - LVPECL Output Termination Circuit 1.5 Input Impairment Monitor This circuit monitors both the input reference signals and reports their status automatically to the DPLL. This block automatically enables ...
Page 9
MS2, MS1 != 10 RESET == 1 FreeRun Reset MS2, MS1 == 10 forces unconditional return from any state to FreeRun Notes equal != : not equal &= : AND operation 0 --> transition from ...
Page 10
Free-Run State The Free-run state is entered when synchronization to the network is not required or is not possible. Typically this occurs during installation, repairs or when a Network Element operates as a master node in an isolated network. ...
Page 11
DPLL to move into and out of the Auto Holdover state. The ZL30462 State Machine may also be driven by controlling the mode select pins MS2, MS1. To avoid network synchronization problems, the State Machine has built-in basic protection ...
Page 12
Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL The Normal to Auto-Holdover to Normal transition will usually happen when the Network Element loses its single reference clock unexpectedly or when it has two references but switching to the ...
Page 13
MS2, MS1 != 10 RESET == 1 FreeRun Reset MS2, MS1 == 10 forces unconditional return from any state to FreeRun Figure 8 - Entry into Auto Holdover state and recovery into Normal mode by switching The new reference ...
Page 14
Two types of transitions are possible: • Semi-automatic transition, which involves changing the RSEL input to select the other reference clock, without changing the mode select inputs MS2, MS1 = 00 (Normal mode). This forces ZL30462 to momentarily transition through ...
Page 15
Characteristics 3.1 AC and DC Electrical Characteristics Absolute Maximum Ratings* Parameter 1 Supply Voltages 2 Input Voltage * Voltages are with respect to ground (GND) unless otherwise stated. * Exceeding these values may cause permanent damage. Functional operation under ...
Page 16
AC Electrical Characteristics* Parameter 1 Freerun Mode accuracy 2 Holdover Mode accuracy 3 Lock range 4 Wander Generation 5 Wander Transfer 6 Phase response to input signal interruptions 7 Phase Transients 8 Holdover Entry Phase Transients 9 Lock Time * ...
Page 17
AC Electrical Characteristics - Input Phase Alignment Characteristics 1 8 kHz ref. pulse width high 2 8 kHz ref. input to F16o delay 3 1.544 MHz ref. pulse width high 4 1.544 MHz ref. input to F16o delay 5 2.048 ...
Page 18
AC Electrical Characteristics - Input Control Signals Characteristics 1 Input Controls Setup Time 2 Input Controls Hold Time /F16o MS1, MS2, RSEL, Figure 13 - Input Control Signal Setup and Hold Time AC Electrical Characteristics - Outputs Timing Characteristics 1 ...
Page 19
JA19Mo tc = 51.44ns /C16o tc = 61.035ns C8o tc = 122.07ns C2o tc = 488.28ns Figure 14 - Output Timing ZL30462 t J19D t C16D t C8D t C2D 18 Zarlink Semiconductor Inc. Data Sheet ...
Page 20
Performance Characteristics Performance Characteristics: Measured Output Jitter - GR-253-CORE and T1.105.03 conformance* Telcordia GR-253-CORE and ANSI T1.105.03 Jitter Generation Requirements Jitter Interface Measurement Filter 1 OC-12 12 kHz to 5 MHz 622.08 Mbit/s (Category II) 2 OC-3 65 kHz ...
Page 21
Performance Characteristics: Measured Output Jitter - G.813 conformance - Option 1 ITU-T G.813 Jitter Generation Requirements Jitter Interface Measurement Filter 1 STM-4 250 kHz to 622.08 Mbit/s 5 MHz 2 STM-1 65 kHz to 155.54 Mbit/s 1.3 MHz 3 E1 ...
Page 22
Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE --- ACN 15 Oct 03 DATE APPRD. Package Code Previous package codes ...
Page 23
For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...