ZL30462MCF ZARLINK [Zarlink Semiconductor Inc], ZL30462MCF Datasheet - Page 6

• Manufacturer Part Number: ZL30462MCF
• Description: Vibratto-S DVD Processor Product Brief
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

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Table 2 shows how each of these modes can be selected via the external hardware pins MS1 and MS2.
Within the DPLL there are a number of key components, which include a Phase Detector, Limiter, Loop Filter,
Digitally Controlled Oscillator, Clock Synthersizer and Lock Indicator.
1.3.1
The Phase Detector compares the virtual reference signal from the TIE Corrector circuit, with its internal input
frequency select circuit and provides an error signal corresponding to the phase difference between the two. This
error signal is passed to the Limiter circuit.
1.3.2
The Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all input
transient conditions with a maximum output phase slope of 41 ns per 1.326 ms.
1.3.3
In Normal mode, the clocks generated by the ZL30462 are phase-locked to the input reference signal. The DPLL
Loop Filter is similar to a first order low pass filter with a 1.5 Hz cutoff frequency for all four reference frequency
selections (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz). This filter ensures that the wander transfer requirements
in ETS 300 011 and AT&T TR62411 are met.
1.3.4
The DCO receives the limited and filtered signal from the Loop Filter, and based on its value, generates a
corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the
ZL30462.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In Holdover Mode, the DCO is free running at a frequency equal to the last (30 ms to 60 ms) frequency the DCO
was generating while in Normal Mode.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSC 20 MHz source.
In Free-run Mode, the Core PLL locks to the 20 MHz Master Clock Oscillator (OSC). The stability of the
generated clock remains the same as the stability of the Master Clock Oscillator.
In Normal Mode, the Core PLL locks to one of the input reference clocks. Both inputs provide preprocessed
phase data to the Core PLL including detection of reference clock quality. This preprocessing reduces the
load on the Core PLL and improves quality of the generated clock.
In Holdover mode, the Core PLL generates a clock based on data collected from past reference signals. The
Core PLL enters Holdover mode if the selected reference input is lost, or under external hardware control.
MS2
0
0
1
1
Phase Detector
Limiter
Loop Filter
Digitally Controlled Oscillator (DCO)
MS1
0
1
0
1
Normal mode
Holdover mode
FreeRun mode
Reserved
Table 2 - Operating Modes
Zarlink Semiconductor Inc.
ZL30462
5
Mode of Operation
Data Sheet