MT90823AL1 ZARLINK [Zarlink Semiconductor Inc], MT90823AL1 Datasheet
MT90823AL1
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MT90823AL1 Summary of contents
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... HCLK Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved. MT90823AP MT90823AL MT90823AB MT90823AG MT90823AB1 MT90823AP1 MT90823AL1 Applications • Medium and large switching platforms • CTI application • Voice/data multiplexer • ...
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Description The MT90823 Large Digital Switch has a non-blocking switch capacity of: 2,048 x 2,048 channels at a serial bit rate of 8.192 Mb/s; 1,024 x 1,024 channels at 4.096 Mb/s; and 512 x 512 channels at 2.048 Mb/s. The ...
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STi0 STi1 13 STi2 STi3 15 STi4 STi5 17 STi6 STi7 19 STi8 STi9 21 STi10 STi11 23 STi12 STi13 25 STi14 STi15 27 F0i FE/HCLK 29 VSS CLK 31 VDD ...
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MT90823 VSS VSS STo14 STo12 STo10 STo9 B VSS VSS STo15 STo13 STo11 STo8 C STi1 VSS VDD VSS VDD STi0 D STi3 VDD STi2 E STi5 VSS STi4 TOP VIEW F ...
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Pin Description Pin # 84 100 100 120 PLCC MQFP LQFP BGA 1, 11, 31, 41, 28, A1,A2,A12,A13, 30, 54 56, 66, 38, B1,B2,B7,B12, 64, 75 76, 99 53, B13,C3,C5,C7, 63, C9,C11,E3,E11 73, G3,G11,J3,J11, 96 L3,L5,L7,L9,L11, M1,M2,M12,M13 2, 32, 5, ...
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Pin Description (continued) Pin # 84 100 100 120 PLCC MQFP LQFP BGA 14-21 ...
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Pin Description (continued) Pin # 84 100 100 120 PLCC MQFP LQFP BGA M10 N12 M11 N13 55 - 32- L12,L13,K12 K13,J12,J13, H12,H13 65 ...
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Pin Description (continued) Pin # 84 100 100 120 PLCC MQFP LQFP BGA B11 77 - 58- A11,B10,A10,B9 A9,A8,B8, 30, 27, 51 ...
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Functional Description A functional Block Diagram of the MT90823 is shown in Figure 1. Data and Connection Memory For all data rates, the received serial data is converted to parallel format by internal serial-to-parallel converters and stored sequentially in the ...
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The MT90823 provides two different interface timing modes controlled by the WFPS pin. If the WFPS pin is low, the MT90823 is in ST-BUS/GCI mode. If the WFPS pin is high, the MT90823 is in the wide frame pulse (WFP) ...
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Serial Interface Data Rate 2 Mb/s 4 Mb/s 8 Mb/s Input Frame Offset Selection Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e., F0i). This ...
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If the LPBK bit is high, the associated ST-BUS output channel data is internally looped back to the ST-BUS input channel (i.e., data from STo n channel m will appear in STi n channel M). Note: when LPBK is activated ...
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Input Rate 2.048 Mb (n-m) time-slots 4.096 Mb (n-m) time-slots 8.192 Mb/s 128 - (n-m) time-slots Input Rate 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s Table 3 - Constant Throughput Delay Value For multiplexed operation, the 8-bit ...
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The data in the control register consists of the memory block programming bit (MBP), the memory select bit (MS) and the stream address bits (STA). The memory block programming bit allows users to program the entire connection memory block, (see ...
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(Note ...
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Initialization of the MT90823 During power up, the TRST pin should be pulsed low, or held low continuously, to ensure that the MT90863 is in the normal functional mode pull-down resistor can be connected to this pin so ...
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Read/Write Address: 01 Reset Value: 0000 Bit Name 15-10 Unused Must be zero for normal operation. 9-5 BPD4-0 Block Programming Data. These bits carry the value to be loaded into ...
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Read Address: 02 Reset Value: 0000 CFE FD11 0 Bit Name Unused Must be zero for normal operation. 12 CFE Complete Frame Evaluation. When CFE = 1, the frame evaluation ...
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ST-BUS Frame CLK Offset Value Input GCI Frame CLK Offset Value Input Figure 4 - Example for Frame Alignment Measurement MT90823 (FD[10: ...
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Read/Write Address Reset value: 0000 OF32 OF31 OF30 DLE3 OF22 OF72 OF71 OF70 DLE7 OF62 OF112 OF111 OF110 DLE11 OF102 15 ...
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Input Stream Offset No clock period shift (Default) + 0.5 clock period shift +1.0 clock period shift +1.5 clock period shift +2.0 clock period shift +2.5 clock period shift +3.0 clock period shift +3.5 clock period shift +4.0 clock period ...
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V/C MC CSTo OE LPBK Bit Name 15 LPBK Per Channel Loopback. This bit should be use for diagnostic purpose only. Set this bit to zero for normal operation. When loopback bit is set for ...
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JTAG Support The MT90823 JTAG interface conforms to the IEEE 1149.1 Boundary-Scan standard and the Boundary-Scan Test (BST) design-for-testability technique it specifies. The operation of the boundary-scan circuitry is controlled by an external test access port (TAP) Controller. Test Access ...
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Test Data Register As specified in IEEE 1149.1, the MT90823 JTAG Interface contains three test data registers: • The Boundary-Scan Register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary ...
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MT90823 Boundary Scan Bit 0 to Bit 117 Output Device Pin Tristate Scan Control Cell STo7 0 1 STo6 2 3 STo5 4 5 STo4 6 7 STo3 8 9 STo2 10 11 STo1 12 13 STo0 14 15 ODE ...
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MT90823 Boundary Scan Bit 0 to Bit 117 Output Device Pin Tristate Scan Control WFPS RESET CLK FE/HCLK F0i STi15 STi14 STi13 STi12 STi11 STi10 STi9 STi8 STi7 STi6 STi5 STi4 STi3 ...
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Applications Switch Matrix Architectures The MT90823 is an ideal device for medium to large size switch matrices where voice and grouped data channels are transported within the same frame. In such applications, the voice samples have to be time interchanged ...
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STi0 STi1 STi2 STi15 FP STi0 FP STi1 FP STi2 FP STi15 Note: 1. Use the external mux to select one of the serial frame pulses start a measurement cycle, set the Start Frame Evaluation (SFE) bit in ...
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Each line represents a stream TC0 that consists of E1 128 channels at 8.192 Mb E1/ Trunk Card TC1 E1/T1 E1 Trunk Card 15 64 input streams TC31 64 output streams ...
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DSTo E1 E1/T1 Trunk 0 DSTi 0 DSTo E1 E1/T1 Trunk 1 DSTi 1 DSTo E1 E1/T1 Trunk 7 DSTi 7 Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any 3.3 V Tolerant pin I/O (other than supply ...
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DC Electrical Characteristics - Characteristics Mb/s Supply Current @ Input High Voltage Input Low Voltage Input Leakage (input pins) S Input Leakage (with pull-up ...
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AC Electrical Characteristics - Frame Pulse and CLK Characteristic 1 Frame pulse width (ST-BUS, GCI) Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s 2 Frame Pulse Setup time before CLK falling (ST-BUS or ...
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AC Electrical Characteristics - Serial Streams for ST-BUS and GCI Backplanes Characteristic 1 Sti Set-up Time 2 Sti Hold Time 3 Sto Delay - Active to Active 4 STo delay - Active to High-Z 5 Sto delay - High-Z to ...
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F0i t FPS CLK STo Bit 7, Last Ch (Note1) STi Bit 7, Last Ch (Note1) Note 1: 2 Mb/s mode, last channel = ch 31, 4 Mb/s mode, last channel = ch 63, 8 Mb/s mode, last channel = ...
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MT90823 CLK V (ST-BUS or) (WFPS mode) CLK V (GCI mode HiZ Valid Data STo t ZD Valid Data HiZ STo t XCD CSTo Figure 14 - Serial Output and External Control ODE t t ODE ODE Valid ...
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AC Electrical Characteristics - Multiplexed Bus Timing (Mode 1) Characteristics 1 ALE pulse width 2 Address setup from ALE falling 3 Address hold from ALE falling 4 RD active after ALE falling 5 Data setup from DTA Low on Read ...
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ALW ALE t t ADS ADH AD0-AD7 HiZ ADDRESS D8-D15 t ALRD CS t CSR CSW t ALWR DTA Figure 16 - Multiplexed Bus Timing (Mode 1) MT90823 HiZ DATA ...
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AC Electrical Characteristics - Multiplexed Bus Timing (Mode 2) Characteristics 1 AS pulse width 2 Address setup from AS falling 3 Address hold from AS falling 4 Data setup from DTA Low on Read 5 CS hold after DS falling ...
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DS R/W AS AD0-AD7 HiZ D8-D15 WR AD0-AD7 D8-D15 HiZ RD CS DTA Figure 17 - Multiplexed Bus Timing (Mode2) MT90823 t RWS t t DSH ASW t t ADS ADH t SW HiZ ADDRESS HiZ ADDRESS t CSS t ...
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AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS rising 6 ...
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DS CS R/W A0-A7 AD0-AD7 D8-D15 READ AD0-AD7 D8-D15 WRITE DTA Figure 18 - Motorola Non-Multiplexed Bus Timing MT90823 t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t t DSW SWD VALID WRITE DATA t DDR t ...
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Zarlink Semiconductor 2002 All rights reserved. 1 ISSUE ACN 213934 20Jan03 DATE APPRD. Package Code : GA Previous package codes: ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...