MT90823AL1 ZARLINK [Zarlink Semiconductor Inc], MT90823AL1 Datasheet - Page 13

• Manufacturer Part Number: MT90823AL1
• Description: 3V Large Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

For multiplexed operation, the 8-bit data and address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address
latch enable (AS/ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W / WR), Chip select (CS) and Data
transfer acknowledge (DTA) signals are required. See Figure 13 and Figure 14 for multiplexed parallel microport
timing.
For the Motorola non-multiplexed bus, the 16-bit data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4
control lines (CS, DS, R/W and DTA) signals are required. See Figure 15 for Motorola non- multiplexed microport
timing.
The MT90823 microport provides access to the internal registers, connection and data memories. All locations
provide read/write access except for the data memory and the frame alignment register which are read only.
Memory Mapping
The address bus on the microprocessor interface selects the MT90823 internal registers and memory. If the A7
address input is low, then the control (CR), interface mode selection (IMS), frame alignment (FAR) and frame input
offset (FOR) registers are addressed by A6 to A0 as shown in Table 4.
If the A7 address input is high, then the remaining address input lines are used to select up to 128 memory
subsection locations. The number selected corresponds to the maximum number of channels per input or output
stream. The address input lines and the stream address bits (STA) of the control register allow access to the entire
data and connection memories.
The control and IMS registers together control all the major functions of the device. The IMS register should be
programmed immediately after system power-up to establish the desired switching configuration (see “Serial Data
Interface Timing” and “Switching Configurations” ).
The control register controls switching operations in the MT90823. It selects the internal memory locations that
specify the input and output channels selected for switching.
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Input Rate
Input Rate
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
128 - (n-m) time-slots
32 - (n-m) time-slots
64 - (n-m) time-slots
Table 3 - Constant Throughput Delay Value
Table 2 - Variable Throughput Delay Value
m < n
Zarlink Semiconductor Inc.
Delay for Variable Throughput Delay Mode
MT90823
(m - output channel number)
13
(n - input channel number))
m-n + 128 time-slots
m-n + 32 time-slots
m-n + 64 time-slots
Delay for Constant Throughput Delay Mode
m = n, n+1, n+2
128 + (128 - n) + (m- 1) time-slots
32 + (32 - n) + (m - 1) time-slots
64 + (64 - n) + (m- 1) time-slots
(m - output channel number)
(n - input channel number))
m-n time-slots
m-n time-slots
m-n time-slots
m > n+2
Data Sheet