ZL50016 ZARLINK [Zarlink Semiconductor Inc], ZL50016 Datasheet - Page 18

• Manufacturer Part Number: ZL50016
• Description: Enhanced 1 K Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

The ZL50016 accepts positive and negative ST-BUS/GCI-Bus input clock and input frame pulse formats via the
programming of CKINP (bit 8) and FPINP (bit 7) in the Control Register (CR). By default, the device accepts the
negative input clock format and ST-BUS format frame pulses. However, the switch can also accept a positive-going
clock format by programming CKINP (bit 8) in the Control Register (CR). A GCI-Bus format frame pulse can be
used by programming FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR).
16.384 Mbps or 8.192 Mbps
4.096 Mbps
2.048 Mbps
Highest Input Data Rate
FPi (244 ns)
FPINP = 0
FPINPOS = 0
FPi (244 ns)
FPINP = 1
FPINPOS = 0
FPi (244 ns)
FPINP = 0
FPINPOS = 1
FPi (244 ns)
FPINP = 1
FPINPOS = 1
CKi
(4.096 MHz)
CKINP = 0
CKi
(4.096 MHz)
CKINP = 1
STi
(2.048 Mbps)
Table 2 - CKi and FPi Configurations for Multiplied Clock Mode
Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the CR
0
CKIN 1-0 Bits
Channel 0
7
00
01
10
Zarlink Semiconductor Inc.
ZL50016
6
18
Input Clock Rate (CKi)
16.384 MHz
8.192 MHz
4.096 MHz
1
Channel 31
0
8 kHz (61 ns wide pulse)
8 kHz (122 ns wide pulse)
8 kHz (244 ns wide pulse)
Input Frame Pulse (FPi)
7
Data Sheet