ZL50051 ZARLINK [Zarlink Semiconductor Inc], ZL50051 Datasheet - Page 48

• Manufacturer Part Number: ZL50051
• Description: 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.8
Address 1001
This register allows the bit rate of all the input and output streams to be set to 8.192 or 16.384 Mbps.
The BRR register is configured as follows:
15:1
Bit
Bit
0
1
0
Bit Rate Register
Reserved
Reserved
BISTCCL
BISTPCL
Name
Name
H
Reset
Value
Reset
Value
Table 23 - Memory BIST Register (MBISTR) Bits (continued)
0
0
0
0
Reserved
Must be set to 0 for normal operation
Bit Rate Selector
This bit defines the bit rate of all the input and output ST-BUS streams, which can
operate at either 8.192 or 16.384 Mbps.
When LOW, 32 Backplane input/output pairs (BSTi[31:0], BSTo[31:0]) and
32 Local input/output pairs (LSTi[31:0], LSTo[31:0]) operate at 8.192 Mbps.
When HIGH, 16 Backplane input/output pairs (BSTi[15:0], BSTo[15:0]) and
16 Local input/output pairs (LSTi[15:0], LSTo[15:0]) operate at 16.384 Mbps.
Local Connection Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Local Connection
Memory BIST sequence.
Local Connection Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Local
Connection Memory BIST sequence (indicated by assertion of BISTCCL).
A HIGH indicates Pass, a LOW indicates Fail.
Table 24 - Bit Rate Register (BRR) Bits
Zarlink Semiconductor Inc.
ZL50051/3
48
Description
Description
Data Sheet