ZL50057 ZARLINK [Zarlink Semiconductor Inc], ZL50057 Datasheet - Page 18

• Manufacturer Part Number: ZL50057
• Description: 12 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 48 Inputs and 48 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
D0 - D15
CS
DS
R/W
DTA
RESET
Pin Name
V10, Y9, W9,
V9, U9, Y8,
W8, V8, W7,
V7, U7, Y6,
W6, V6, Y5,
W5
B11
A11
C11
A13
C12
Coordinates
Package
(272-ball
ZL50057
PBGA)
M9, M8, M7,
M6, N9, N8,
N7, N6, P9,
P8, P7, P6,
R9, R8, R7,
R6
A8
A6
A7
C10
B11
Coordinates
Package
(256-ball
ZL50058
PBGA)
Zarlink Semiconductor Inc.
ZL50057/8
Data Bus 0 - 15 (5 V Tolerant Inputs/Outputs with
Slew-Rate Control). These pins form the 16-bit data bus of
the microprocessor port.
D0 = LSB
Chip Select (5 V Tolerant Input). Active LOW input used by
the microprocessor to enable the microprocessor port access.
Note that a minimum of 30 ns must separate the
de-assertion of DTA (to high) and the assertion of CS
and/or DS to initiate the next access.
Data Strobe (5 V Tolerant Input). This active LOW input
works in conjunction with CS to enable the microprocessor
port read and write operations. Note that a minimum of
30 ns must separate the de-assertion of DTA (to high) and
the assertion of CS and/or DS to initiate the next access.
Read/Write (5 V Tolerant Input). This input controls the
direction of the data bus lines (D0-D15) during a
microprocessor access.
Data Transfer Acknowledgment (5 V Tolerant Three-state
Output). This active LOW output indicates that a data bus
transfer is complete. A pull-up resistor is required to hold a
HIGH level. Note that a minimum of 30 ns must separate
the de-assertion of DTA (to high) and the assertion of CS
and/or DS to initiate the next access.
Device Reset (5 V Tolerant Input with Internal Pull-up).
This input (active LOW) asynchronously applies reset and
synchronously releases reset to the device. In the reset state,
the outputs LSTo0-15 and BSTo0-31 are set to a HIGH or high
impedance state, depending on the state of the LORS and
BORS external control pins, respectively. The assertion of
RESET causes the LCSTo0-1 and BCSTo0-3 pins to be driven
LOW (refer to Table 2). The assertion of this pin also clears
the device registers and internal counters. Refer to
Section 8.3 on page 55 for the timing requirements
regarding this reset signal.
18
Description
Data Sheet