ZL50057 ZARLINK [Zarlink Semiconductor Inc], ZL50057 Datasheet - Page 38

• Manufacturer Part Number: ZL50057
• Description: 12 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 48 Inputs and 48 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.2
Note that when the devices are operating in Local 32 Mbps mode, some of the output streams (the upper half of the
available streams) are unused. The LE bits of the channels on those output streams will always be low. Therefore,
the upper LSTo pins are either driven HIGH or high impedance, in accordance with the value of the LORS input
signals, as shown in Table 2 on page 33.
The data (channel control bit) transmitted by LCSTo0-1 replicates the Local Output Enable (LE) bit of the Local
Connection Memory, with a LOW state indicating the channel to be set to high impedance. Refer to “Local
Connection Memory Bit Definition,” on page 60 for more details.
The LCSTo0-1 pins transmit serial data (channel control bits) at 16.384 Mbps, with each bit representing the
per-channel high impedance state for a specific stream. Four output streams are allocated to each control line as
follows:
•
•
The channel control bit location, within a frame period, for each channel of the Local output streams is presented in
Table 4, LCSTo Allocation of Channel Control Bits to Output Streams (32 Mbps Mode)
The LCSTo0-1 pins output data at a constant data rate of 16.384Mbps and all output streams, LSTo0-7, operate at
a data rate of 32.768 Mbps.
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 4:
1. The channel control bit corresponding to Stream 0, Channel 0, LSTo0_Ch0, is transmitted on LCSTo0 and is
2. The channel control bit corresponding to Stream 6, Channel 0, LSTo6_Ch0, is transmitted on LCSTo0 in
3. For stream LSTo2, the value of the channel control bit for Channel 511 will be transmitted during the C16o clock
4. For stream LSTo3, the value of the channel control bit for Channel 5 will be transmitted during the C16o clock
LCSTo0 outputs the channel control bits for streams L/BSTo0, 2, 4, and 6.
LCSTo1 outputs the channel control bits for streams L/BSTo1, 3, 5, and 7.
advanced, relative to the frame boundary, by ten periods (clock period no. 2039) of C16o.
advance of the frame boundary by seven periods (clock period no. 2042) of output clock, C16o. Similarly, the
channel control bits for LSTo7_Ch0 are advanced relative to the frame boundary by seven periods of C16o on
LCSTo1.
period no. 2036 on LCSTo0.
period no. 12 on LCSTo1.
LORS Asserted LOW, 32Mbps Mode
Zarlink Semiconductor Inc.
ZL50057/8
38
Data Sheet