ZL50060 ZARLINK [Zarlink Semiconductor Inc], ZL50060 Datasheet - Page 48

• Manufacturer Part Number: ZL50060
• Description: 16 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 64 Inputs and 64 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

9.2
The Backplane Connection Memory (BCM) is a 16-bit wide memory with 8,192 memory locations to support the
Backplane output port. The most significant bit of each word, bit[15], selects the source stream from either the
Backplane (BSRC = HIGH) or the Local (BSRC = LOW) port and determines the Local-to-Backplane or
Backplane-to-Backplane data routing. Bit[14:13] select the control modes of the Backplane output streams, namely
the per-channel Message Mode and the per-channel high impedance output control mode. In Connection Mode
(bit[14] = LOW), bits[12:0] select the source stream and channel number as detailed in Table 8. In Message Mode
(bit[14] = HIGH), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. Bit[13] must be
HIGH for Message Mode to ensure that the output channel is not tri-stated.
The Control Register bits MS[2:0] must be set to 000 to select the Local Connection Memory for the write and read
operations via the microprocessor port. The Control Register bits MS[2:0] must be set to 001 to select the
Backplane Connection Memory for the write and read operations via the microprocessor port. See Section 7.0,
Microprocessor Port, and Section 14.1, Control Register (CR) for details on microprocessor port access.
9.3
This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after
power-up. When the Memory Block Programming mode is enabled, the contents of the Block Programming
Register (BPR) will be loaded into the connection memories. See Table 19 and Table 20 for details of the Control
Register and Block Programming Register values, respectively.
9.3.1
•
•
LBPD2
Set the MBP bit in the Control Register from LOW to HIGH.
Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,
LBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] of the Local Connection
Memory. The remaining bit positions are loaded with zeros as shown in Table 9.
15
Backplane Connection Memory
Connection Memory Block Programming
Memory Block Programming Procedure:
LBPD1
Source Stream Bit Rate
14
Table 9 - Local Connection Memory in Block Programming Mode
Table 8 - Local and Backplane Connection Memory Configuration
16 Mbps
32 Mbps
2 Mbps
4 Mbps
8 Mbps
LBPD0
13
12
0
11
0
Zarlink Semiconductor Inc.
Source Stream No.
legal values 0:31
legal values 0:31
legal values 0:31
legal values 0:31
legal values 0:15
10
ZL50060/1
0
Bits[12:8]
Bits[12:8]
Bits[12:8]
Bits[12:8]
Bits[12:9]
9
0
48
8
0
7
0
6
0
Source Channel No.
legal values 0:127
legal values 0:255
legal values 0:511
legal values 0:31
legal values 0:63
5
0
Bits[7:0]
Bits[7:0]
Bits[7:0]
Bits[7:0]
Bits[8:0]
4
0
3
0
2
0
Data Sheet
1
0
0
0