ZL50070GAC ZARLINK [Zarlink Semiconductor Inc], ZL50070GAC Datasheet
ZL50070GAC
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ZL50070GAC Summary of contents
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... Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16 Mbps), and 96 Inputs and 96 Outputs ZL50070GAC ZL50070GAG2 **Pb Free Tin/Silver/Copper • Per-channel constant or variable throughput delay for frame integrity and low latency applications • ...
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Applications • Large Switching Platforms • Central Office Switches • Wireless Base Stations • Multi-service Access Platforms • Media Gateways Description The ZL50070 is a non-blocking Time Division Multiplex (TDM) switch with maximum 24,576 x 24,576 channels. The device can ...
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Group Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - ZL50070 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Data Rate and Maximum Switch Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Change Summary The following table captures the changes from the April 2005 issue. Page Item 28 10.4.1, “Read Cycle“ 29 Figure 10 "Read Cycle Operation" 29 10.4.2, “Write Cycle“ 30 Figure 11 "Write Cycle Operation" 41 Table 23 “BER Counter ...
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Pin Diagram - 484 Ball PBGA (as viewed through top of package) A1 corner identified by metallized marking CKo STiA D[30] D[25] D[20] D[16] D[15] D[11] A [0] [0] ...
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Pin Description Pin F7, F10, F13, F17, G9, G12, V DD_CORE G15, H6, H10, H13, H16, J7, K8, K15, K17, L6, L16, M7, N8, N15, P6, P16, P17, R7, R10, R13, T9, T12, T15, U10, U13, U17 F9, F12, F15, ...
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Pin Description (continued) Pin D6, F5, E3, D1, J3, L5, M3, STiC0-23 M4, U1, U3, AA1, AA2, V7, W8, AB6, V10, AB11, Y14, AB18, U16, AB21, W20, U20, P19 C4, B2, D2, H3, E1, K2, L4, STiD0-23 R1, V1, T4, ...
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Pin Description (continued) Pin D4, F4, G3, G2, G1, L2, N3, SToD0-23 T1, U2, T6, V5, AA3, W7, AA7, W10, Y11, Y12, AB17, AA18, W18, V19, AA22, U21, N17 W12 AA13 J2, G21 CKi1-2 K3, K19 FPi1-2 ZL50070 Name Serial ...
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Pin Description (continued) Pin A1, AB4, R18, E14 CKo0-3 G5, Y6, T19, C17 FPo0-3 W15, V14 CK_SEL0-1 L1 A18, B20, B22, C18, C21, C22, D17, D20, E16, E19, E21, E22, F20,F22, G19, G20, G22, H19, H21, H22, J20, J21, K22, ...
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Pin Description (continued) Pin A11, C11, E11, B11, A10, B10, C10, A9, D10, B9, F11, A8, C9, B8, E10, A7, A6, D9, E9, C8, A5, B6, C7, D8, E8, A4, B5, C6, D7, F8, A3, B4 B16, A17, A16, C14, ...
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Pin Description (continued) Pin B18, E15 SIZ0 A20 D18 B21 A22 C19 E17 ZL50070 Name Data Transfer Size/Upper and Lower Data Strobe Inputs (5 V Tolerant Inputs) Motorola 32-bit mode - signals indicate data transfer size, refer to ...
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Functional Description 1.1 Overview The device has 96 ST-BUS/GCI-Bus inputs (STiA0 - 23, STiB0 - 23, STiC0 - 23, STiD0 - 23) and 96 ST-BUS/GCI-Bus outputs (SToA0 - 23, SToB0 - 23, SToC0 - 23, SToD0 - 23). It ...
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Maximum Number TDM Group of Input TDM Data Data Rate Streams 65.536 Mbps 24 32.768 Mbps 48 16.384 Mbps 96 8.192 Mbps 96 Table 1 - Data Rate and Maximum Switch Size † The maximum capacity shown is when all ...
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For 65 Mbps operation, only those inputs and outputs in the TDM ’A’ streams are active. For 32 Mbps operation, only those inputs and outputs in the TDM ’A’ and ’B’ streams are active. For 16 Mbps and 8 Mbps, ...
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Rate Conversion The ZL50070 supports rate conversion from any input stream rate to any output stream rate. An example of ZL50070 rate conversion is given in Figure . Here the total capacity of both the input and the output ...
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CK_SEL1 Table 3 - CKi0 and FPi0 Setting via CK_SEL1 - 0 Two additional input clocks (CKi2 - 1) and frame pulses (FPi2 - 1) can be accepted. These signals can be 8.192 MHz, 16.384 MHz, ...
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Data Input Delay and Data Output Advancement The Group Control Registers (GCR) are used to adjust the input delay and output advancement for each input and output data groups. Each group is independently programmed. 5.1 Input Sampling Point Delay ...
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By default all output streams have zero bit advancement such that bit 7 is the first bit that appears after the output frame boundary (assuming ST-BUS formatting). The output advancement is enabled by the Output Stream Bit Advancement (bits 21 ...
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Message Mode In Message Mode (MSG), microprocessor data can be broadcast to the output data streams on a per-channel basis. This feature is useful for transferring control and status information to external circuits or other TDM devices. For a ...
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N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 Figure 7 - Data Throughput Delay for Constant Delay 7.2 Variable Delay Mode Variable delay mode ...
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Per-Channel A-Law/ The ZL50070 provides per channel code translation to be used to adapt pulse code modulation (PCM) voice or data traffic between networks which use different encoding laws. Code translation is available in both Connection Modes and ...
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Frame m Figure 9 - Example PRBS Timeslot Insertion Each PRBS detector can be configured to monitor for bit errors in one or more timeslots. The selection of timeslots is configured by the Input BER Enable Control ...
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Address (Hex) Table 5 - Example of Address and Byte Significance 10.2 32 Bit Bus Operation In 32 bit mode (D16B = 0), all 32 bits of the Data Bus, D31 - 0, may be used for write and read ...
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Bit Bus Operation In 16 bit mode (D16B = 1), D15 - 0 are used for data transfers to/from the ZL50070. D31 - 16 are unused and must be connected to a defined logic level. D15 on the ...
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Address Register (Hex) Description 40200 or Group Control Register (Group 0) 40201 40282 or Input Clock Control Register 40283 40286 or Output Clock Control Register 40287 40284 or Output Clock Control Register 40285 Table Bit Mode Example ...
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Address A, SIZ1 - 0 CS R/W DS Hi-Z Data DTA Hi-Z BERR Hi-Z WAIT The cycle termination signals WAIT & DTA are provided for all bus configurations 10.4.2 Write Cycle The operation of the write cycle is illustrated in ...
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Address SIZ1 - 0 CS R/W DS Data DTA Hi-Z BERR Hi-Z WAIT The cycle termination signals WAIT & DTA are provided for all bus configurations 11.0 Power-up and Initialization of the ZL50070 11.1 Device Reset and Initialization The PWR ...
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Note: After the PWR reset is removed, and on the application of a suitable master clock input, it takes approximately 1 ms for the internal initialization to complete • Automatic block initialization of the Connection Memory to all zeros occurs, ...
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Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to V driven from an external source. When JTAG is not in use, this pin must be tied low for normal operation. The TAP signals ...
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Address (Hex) 36000 - 3FFFF Invalid Address. Access causes Bus error (BERR) 40000 - 4017F BER Counters 40180 - 401FF Invalid Address. Access causes Bus error (BERR) 40200 - 4025F Group Control Registers 40260 - 4027F Invalid Address. Access causes ...
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Start Output Address Group (Hex) 10 00A000 11 00B000 Table 13 - Connection Memory Group Address Mapping (continued) The mapping of each output stream, SToAn, SToBn, SToCn and SToDn, depends on the programmed bit rate. The address offset range for ...
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ZL50070 Timeslot SToAn SToBn SToCn 128 128 129 129 - - 254 254 255 255 256 256 257 257 - - 510 510 511 511 512 513 - 1021 1022 1023 Table 15 - Connection Memory Timeslot Address Offset Range ...
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Connection Memory Bit Functions The bit functions of the connection memory are illustrated in Table 16. External Read/Write Address: 000000 -017FFF H Reset Value: 0000 PCF PCF PCF ICL V ...
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External Read/Write Address: 000000 -017FFF H Reset Value: 0000 PCF PCF PCF ICL V Bit Name ...
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Start Output Address Group (Hex) 0 020000 1 020400 2 020800 3 020C00 4 021000 5 021400 6 021800 7 021C00 8 022000 9 022400 10 022800 11 022C00 Table 17 - Connection Memory LSB Group Address Mapping Output Group ...
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Data Memory The data memory field is a read only address range used to monitor the data being received by the input streams. Addressing into each of the streams is illustrated in Table 19. Start Input Address Group (Hex) ...
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The entire data memory is a read only structure. Any write attempts will result in a bus error. BERR ...
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Input Group Data Rate Time-slot Range 8 Mbps Table 22 - BER Enable Control Memory Stream Address Offset at Various Output Rates (continued) 14.3.2 BER Counters There are a total of 96 Bit Error Counters, corresponding to the 96 serial ...
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Group Control Registers The ZL50070 addresses the issues of a simple programming model and automatic stream configuration by defining a basic switching bit rate of 65.536 Mbps and by grouping the I/O streams. Each TDM I/O group contains 4 ...
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External Read/Write Address: 40200 - 4025F H Reset Value: 000C000C Bit Name ...
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External Read/Write Address: 40200 - 4025F H Reset Value: 000C000C Bit Name ...
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Input Clock Control Register The Input Clock Control Register is used to select the logic sense of the input clock. External Read/Write Address: 40280 -40283 H Reset Value: 0DB ...
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Output Clock Control Register The Output Clock Control Register is used to select the desired source, frequency, and logic sense of the output clocks. The bit functions of the Output Clock Control Register are illustrated in Table 27. External ...
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External Read/Write Address: 40284 -40287 H Reset Value: 060D1C3C GCO SEL3 CKO2 CKO2 GCO FPO CKO SRC1 SRC0 SEL1 POL1 POL1 Bit Name 20 GCO ...
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External Read/Write Address: 40284 -40287 H Reset Value: 060D1C3C GCO SEL3 CKO2 CKO2 GCO FPO CKO SRC1 SRC0 SEL1 POL1 POL1 RATE1 Bit Name 12 ...
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External Read/Write Address: 40284 -40287 H Reset Value: 060D1C3C GCO SEL3 CKO2 CKO2 GCO FPO CKO SRC1 SRC0 SEL1 POL1 POL1 Bit Name 4 CKO ...
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Block Init Enable Register The Block Init Enable Register bit read/write register at address 04028C - 04028F The Block Init Enable Register is used to initiate a block initialization of the connection memory. A block initialization ...
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DC/AC Electrical Characteristics 1 Absolute Maximum Ratings - Voltages are with respect to ground (V Characteristics 1 Chip I/O Supply Voltage 2 Chip Core Supply Voltage 3 Input Voltage (non-5 V tolerant inputs) 4 Input Voltage (5 V tolerant ...
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DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 10 Pull-down Current 11 Input Pin Capacitance 12 Output High Voltage 13 Output Low Voltage Note 1: Typical figures are at 25°C, V DD_CORE subject ...
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AC Electrical Characteristics - FPi0-2 and CKi0-2 Timing No. Characteristic (Figure ) 4 CKi0-2 Input Clock Period (average value, does not consider the effects of jitter) 5 CKi Input Clock High Time 6 CKi Input Clock Low Time 7 ...
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AC Electrical Characteristics - FPi and CKi Skew No. Characteristic (Figure 13) 1 CKi0 to CKi1, 2 Skew Note 1: Characteristics are over recommended operating conditions unless otherwise stated. Note 2: Typical figures are at 25°C, V DD_CORE subject ...
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AC Electrical Characteristics - FPO0-3 and CKO0-3 (65.536 MHz) Timing No. Characteristic 1 FPO0-3 Output Frame Pulse Setup Time 2 FPO0-3 Output Frame Pulse Hold Time 3 CKO0-3 Output Clock Period 1 AC Electrical Characteristics - FPO0-3 and CKO0-3 ...
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FPo0-3 t FPOS CKo0-3 Output Frame Boundary Figure 14 - ST-Bus Frame Pulse and Clock Output Timing FPo0-3 t FPOS CKo0-3 Output Frame Boundary Figure 15 - GCI Frame Pulse and Clock Output Timing AC Electrical Characteristics - Output Clock ...
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AC Electrical Characteristics - Serial Data Timing No. Characteristic (Figure ) 1 CKi to CKo Positive edge Propagation Delay 2 CKi to CKo Negative edge Propagation Delay 3 STi to posedge CKi setup 4 STi to posedge CKi hold ...
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FPi (negative sense) FPo (negative sense) CKo (negative sense) CKi (negative sense) STin STon STon ODE FPi (negative sense) FPo (negative sense) CKo (positive sense) CKi (positive sense) STin STon STon Note 1: CKi frequency is assumed to be twice ...
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AC Electrical Characteristics - Serial Data Timing No. Characteristic (Figure ) 1 STi to posedge CKo setup 2 STi to posedge CKo hold 3 STi to negedge CKo setup 4 STi to negedge CKo hold 5 Posedge CKo to Output ...
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FPo (negative sense) CKo (negative sense) STin STon STon FPo (negative sense) CKo (positive sense) STin STon STon Note 1 : CKo frequency is assumed to be twice of the STin data rate, so that the sampling point is at ...
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AC Electrical Characteristics - CKo to Other CKo No. Characteristic (Figure 17) 1 CKo1 to CKo0 skew 2 CKo2 to CKo0 skew 3 CKo1 to CKo3 skew 4 CKo2 to CKo3 skew 5 CKo3 to CKo0 skew 6 CKo2 to ...
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AC Electrical Characteristics - Microprocessor Bus Interface No Characteristics (Figure 19, & Figure 19 Recovery 2 CS Recovery 3 CS asserted setup to DS asserted 4 Address, SIZ1-0, R/W setup to DS asserted 5 CS hold from DS ...
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DS t CSRE CS A18-A0 RWN,SIZ D31-D0 READ D31-D0 WRITE Hi-Z DTA BERR Hi-Z WAIT Figure 19 - Microprocessor Bus Interface Timing DS SIZ1-SIZ0 (BE1-BE0 or UDS, LDS) Figure 20 - Intel Mode Timing ZL50070 t DSRE t CSS t ...
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AC Electrical Characteristics - IEEE 1149.1 Test Port and PWR Pin Timing No. Characteristic (Figure 21) 1 TCK Clock Period 2 TCK Clock Frequency 3 TCK Clock Pulse Width High 4 TCK Clock Pulse Width Low 5 TMS Set-up ...
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