ZL50110 ZARLINK [Zarlink Semiconductor Inc], ZL50110 Datasheet - Page 41

• Manufacturer Part Number: ZL50110
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

3.6
All System Function Interface signals are 5 V tolerant.
The core of the chip will be held in reset for 16383 SYSTEM_CLK cycles after SYSTEM_RST has gone HIGH to
allow the PLL’s to lock.
CPU_DREQ0
CPU_DREQ1
CPU_IREQO
CPU_IREQ1
SYSTEM_CLK
SYSTEM_RST
SYSTEM_DEBUG
System Function Interface
Signal
Signal
Table 15 - System Function Interface Package Ball Definition
Table 14 - CPU Interface Package Ball Definition (continued)
OT
OT
I/O
I/O
O
O
I
I
I
AC15
AE16
AF17
AD16
U6
V4
U5
Package Balls
Package Balls
Zarlink Semiconductor Inc.
ZL50110/11/14
41
System Clock Input. The system clock
frequency is 100 MHz. The frequency
must be accurate to within ±32 ppm in
synchronous mode. The quality of
SYSTEM_CLK, or the oscillator that
drives SYSTEM_CLK directly impacts
the adaptive clock recovery
performance. See Section 6.3.
System Reset Input. Active low. The
system reset is asynchronous, and
causes all registers within the
ZL50110/11/14 to be reset to their default
state. Recommend external pull-up.
System Debug Enable. This is an
asynchronous signal that, when
de-asserted, prevents the software
assertion of the debug-freeze command,
regardless of the internal state of
registers, or any error conditions. Active
high. Recommend external pull-down.
CPU DMA 0 Request Output Active low
synchronous to CPU_CLK rising edge.
Asserted by ZL50110/11/14 to request
the host initiates a DMA write. Only used
for DMA transfers, not for normal
register access.
CPU DMA 1 Request
Active low synchronous to CPU_CLK
rising edge. Asserted by ZL50110/11/14
to indicate packet data is ready for
transmission to the CPU, and request
the host initiates a DMA read. Only used
for DMA transfers, not for normal
register access.
CPU Interrupt 0 Request (Active Low)
CPU Interrupt 1 Request (Active Low)
Description
Description
Data Sheet