ATXMEGA384A1-CU ATMEL [ATMEL Corporation], ATXMEGA384A1-CU Datasheet
ATXMEGA384A1-CU
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ATXMEGA384A1-CU Summary of contents
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... Motor control • • Board control Networking • • White Goods Optical 2 C and SMBus compatible) • Hand-held battery applications • Power tools • HVAC • Metering • Medical Applications 8/16-bit XMEGA A1 Microcontroller ATxmega384A1 ATxmega256A1 ATxmega192A1 ATxmega128A1 ATxmega64A1 Preliminary 8067D–AVR–08/08 ...
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... Ordering Code Flash (B) ATxmega384A1-AU 384K + 8K ATxmega256A1-AU 256K + 8K ATxmega192A1-AU 192K + 8K ATxmega128A1-AU 128K + 8K ATxmega64A1-AU 64K + 4K ATxmega384A1-CU 384K + 8K ATxmega256A1-CU 256K + 8K ATxmega192A1-CU 192K + 8K ATxmega128A1-CU 128K + 8K ATxmega64A1-CU 64K + 4K Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. ...
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Figure 2-2. CBGA-pinout Top view Table 2-1. CBGA-pinout PK0 VCC B PK3 PK2 C VCC PK5 D GND PK6 TOSC1/ TOSC2/ ...
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Overview The XMEGA family of low power, high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the AVR instructions in a single clock cycle, the XMEGA A1 achieves throughputs approaching 1 Million Instructions Per Second ...
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Block Diagram Figure 3-1. XMEGA A1 Block Diagram DACA PA[0..7] PORT A (8) ACA ADCA AREFA Internal Reference AREFB ADCB ACB PB[0..7]/ PORT B (8) JTAG DACB IRCOM 8067D–AVR–08/08 PR[0..1] PQ[0..3] XTAL1 TOSC1 XTAL2 TOSC2 Oscillator Circuits/ Clock Generation ...
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... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading • XMEGA A Manual • XMEGA A Application Notes This device data sheet only contains part specific information and a short description of each peripheral and module. The XMEGA A Manual describes the modules and peripherals in depth. ...
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AVR CPU 6.1 Features • 8/16-bit high performance AVR RISC Architecture – 138 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in SRAM • Stack Pointer accessible in I/O memory space • Direct ...
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The program memory is In- System Self-Programmable Flash memory. 6.3 Register File The fast-access Register File contains 32 x 8-bit general purpose working registers with single clock cycle access time. ...
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Memories 7.1 Features • Flash Program Memory – One linear address space – In-System Programmable – Self-Programming and Bootloader support – Application Section for application code – Application Table Section for application code or data storage – Boot Section ...
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The Program Flash memory space is divided into Application and Boot sections. Both sections have dedicated Lock Bits for setting restrictions on write or read/write operations. The Store Pro- gram Memory (SPM) instruction must reside in the Boot Section when ...
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... The XMEGA A1 devices has internal EEPROM memory for non-volatile data storage addressable either in a separate data space or it can be memory mapped into the normal data memory space. The EEPROM memory supports both byte and page access. 8067D–AVR–08/08 Byte Address ATxmega384A1 0 I/O Registers (4KB) FFF ...
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EBI - External Bus Interface • Supports SRAM up to – 512K Bytes using 2-port EBI – 16M Bytes using 3-port EBI • Supports SDRAM up to – 128M bit using 3-port EBI • Four software configurable Chip Selects ...
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... This ensures parameter storage during multiple program/erase ses- sion and On-Chip Debug sessions. 8067D–AVR–08/08 Table 7-1 on page 13. Some of the calibration values will be automatically loaded to Device ID bytes for XMEGA A1 devices. Device ATxmega64A1 ATxmega128A1 ATxmega192A1 ATxmega256A1 ATxmega384A1 XMEGA A1 Device ID bytes Byte 2 Byte ...
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... Table 7-3. Devices EEPROM Size (Bytes) ATxmega64A1 2K ATxmega128A1 2K ATxmega192A1 2K ATxmega256A1 4K ATxmega384A1 4K 8067D–AVR–08/08 shows the Flash Program Memory organization. Flash write and erase Number of words and Pages in the Flash. FWORD FPAGE (words) 128 Z[7:1] Z[16:8] 256 Z[8:1] Z[17:9] ...
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DMAC - Direct Memory Access Controller 8.1 Features • Allows High-speed data transfer – From memory to peripheral – From memory to memory – From peripheral to memory – From peripheral to peripheral • 4 Channels • From 1 ...
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Event System 9.1 Features • Inter-peripheral communication and signalling with minimum latency • CPU and DMA independent operation • 8 Event Channels allows for signals to be routed at the same time • Events can be ...
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Figure 9-1. The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators (ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Com- munication Module (IRCOM). Events can also be generated from software (CPU). All ...
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System Clock and Clock options 10.1 Features • Fast start-up time • Safe run-time clock switching • Internal Oscillators: – 32 MHz run-time calibrated RC oscillator – 2 MHz run-time calibrated RC oscillator – 32 kHz calibrated RC oscillator ...
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Figure 10-1. Clock system overview Each clock source is briefly described in the following sub-sections. 10.3 Clock Options 10.3.1 32 kHz Ultra Low Power Internal Oscillator The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power ...
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Crystal Oscillator The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be used as system clock source or as asynchronous clock source for the Real Time Counter. 10.3.4 0.4 ...
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Power Management and Sleep Modes 11.1 Features • 5 sleep modes – Idle – Power-down – Power-save – Standby – Extended standby • Power Reduction registers to disable clocks to unused peripherals 11.2 Overview The XMEGA A1 provides various ...
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System Control and Reset 12.1 Features • Multiple reset sources for safe operation and device reset – Power-On Reset – External Reset – Watchdog Reset – Brown-Out Reset – JTAG Reset – PDI reset – Software reset • Asynchronous ...
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JTAG reset The MCU is reset as long as there is a logic one in the Reset Register in one of the scan chains of the JTAG system. Refer to IEEE 1149.1 (JTAG) Boundary-scan for details. 12.3.6 PDI reset ...
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PMIC - Programmable Multi-level Interrupt Controller 13.1 Features • Separate interrupt vector for each interrupt • Short, predictable interrupt response time • Programmable Multi-level Interrupt Controller – 3 programmable interrupt levels – Selectable priority scheme within low level interrupts ...
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Table 13-1. Reset and Interrupt Vectors (Continued) Program Address (Base Address) Source 0x040 NVM_INT_base 0x044 PORTB_INT_base 0x048 ACB_INT_base 0x04E ADCB_INT_base 0x056 PORTE_INT_base 0x05A TWIE_INT_base 0x05E TCE0_INT_base 0x06A TCE1_INT_base 0x072 SPIE_INT_vect 0x074 USARTE0_INT_base 0x07A USARTE1_INT_base 0x080 PORTD_INT_base 0x084 PORTA_INT_base 0x088 ACA_INT_base ...
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I/O Ports 14.1 Features • Selectable input and output configuration for each pin individually • Flexible pin configuration through dedicated Pin Configuration Register • Synchronous and/or asynchronous input sensing with port interrupts and events – Sense both edges – ...
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Push-pull Figure 14-1. I/O configuration - Totem-pole 14.3.2 Pull-down Figure 14-2. I/O configuration - Totem-pole with pull-down (on input) 14.3.3 Pull-up Figure 14-3. I/O configuration - Totem-pole with pull-up (on input) 14.3.4 Bus-keeper The bus-keeper’s weak output produces the ...
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Figure 14-4. I/O configuration - Totem-pole with bus-keeper 14.3.5 Others Figure 14-5. Output configuration - Wired-OR with optional pull-down Figure 14-6. I/O configuration - Wired-AND with optional pull-up 8067D–AVR–08/08 DIRn OUTn INn OUTn INn INn OUTn XMEGA ...
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Input sensing • Sense both edges • Sense rising edges • Sense falling edges • Sense low level Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure ...
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T/C - 16-bit Timer/Counter 15.1 Features • Eight 16-bit Timer/Counters – Four Timer/Counters of type 0 – Four Timer/Counters of type 1 • Four Compare or Capture (CC) Channels in Timer/Counter 0 • Two Compare or Capture (CC) Channels ...
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Figure 15-1. Overview of a Timer/Counter and closely related peripherals Timer/Counter Base Counter Timer Period Compare/Capture Channel B Compare/Capture Channel A Comparator The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by 2 bits (4x). This is ...
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AWEX - Advanced Waveform Extension 16.1 Features • Output with complementary output from each Capture channel • Four Dead Time Insertion (DTI) Units, one for each Capture channel • 8-bit DTI Resolution • Separate High and Low Side Dead-Time ...
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Hi-Res - High Resolution Extension 17.1 Features • Increases Waveform Generator resolution by 2-bits (4x) • Supports Frequency, single- and dual-slope PWM operation • Supports the AWEX when this is enabled and used for the same Timer/Counter 17.2 Overview ...
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RTC - 16-bit Real-Time Counter 18.1 Features • 16-bit Timer • Flexible Tick resolution ranging from 32.768 kHz • One Compare register • One Period register • Clear timer on Overflow or Compare Match • Overflow ...
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TWI - Two-Wire Interface 19.1 Features • Four Identical TWI peripherals • Simple yet Powerful and Flexible Communication Interface • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space Allows ...
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SPI - Serial Peripheral Interface 20.1 Features • Four Identical SPI peripherals • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of ...
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USART 21.1 Features • Eight Identical USART peripherals • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High-resolution Arithmetic Baud Rate Generator • Supports Serial ...
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IRCOM - IR Communication Module 22.1 Features • Pulse modulation/demodulation for infrared communication • Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps • Selectable pulse modulation scheme – 3/16 of baud rate period – Fixed ...
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Crypto Engine 23.1 Features • Data Encryption Standard (DES) CPU instruction • Advanced Encryption Standard (AES) Crypto module • DES Instruction – Encryption and Decryption – Single-cycle DES instruction – Encryption/Decryption in 16 clock cycles per 8-byte block • ...
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ADC - 12-bit Analog to Digital Converter 24.1 Features • Two ADCs with 12-bit resolution • 2 Msps sample rate for each ADC • Signed and Unsigned conversions • 4 result registers with individual input channel control for each ...
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Figure 24-1. ADC overview Each ADC has four MUX selection registers with a corresponding result register. This means that four channels can be sampled within 1.5 µs without any intervention by the application other than starting the conversion. The results ...
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DAC - 12-bit Digital to Analog Converter 25.1 Features • Two DACs with 12-bit resolution • Msps conversion rate for each DAC • Flexible conversion range • Multiple trigger sources • 1 continuous output or 2 ...
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AC - Analog Comparator 26.1 Features • Four Analog Comparators • Selectable Power vs. Speed • Selectable hysteresis – mV • Analog Comparator output available on pin • Flexible Input Selection – All pins on ...
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Figure 26-1. Analog comparator overview Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled 8067D–AVR–08/08 XMEGA A1 + Pin 0 output AC0 - Interrupt sensitivity control + AC1 - ...
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Input Selection The Analog comparators have a very flexible input selection and the two comparators grouped in a pair may be used to realize a window function. One pair of analog comparators is shown in Figure 26-1 on page ...
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OCD - On-chip Debug 27.1 Features • Complete Program Flow Control – Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor • Debugging on C and high-level language source code level • Debugging on Assembler and disassembler level ...
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Program and Debug Interfaces 28.1 Features • PDI - Program and Debug Interface (Atmel proprietary 2-pin interface) • JTAG Interface (IEEE std. 1149.1 compliant) • Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG) • Access to the OCD ...
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Pinout and Pin Functions The pinout of XMEGA A1 is shown in I/O functionality, each pin may have several functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the alternate ...
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Timer/Counter and AWEX functions OCnx OCxn 29.1.6 Communication functions SCL SDA SCLIN SCLOUT SDAIN SDAOUT XCKn RXDn TXDn SS MOSI MISO SCK 29.1.7 Oscillators, Clock and Event TOSCn XTALn CLKOUT EVOUT 29.1.8 Debug/System functions RESET PDI_CLK PDI_DATA TCK TDI ...
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Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head ...
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Table 29-3. Port C - Alternate functions PORT C PIN # INTERRUPT GND 13 AVCC 14 PC0 15 SYNC PC1 16 SYNC SYNC/ASY PC2 17 NC PC3 18 SYNC PC4 19 SYNC PC5 20 SYNC PC6 21 SYNC PC7 22 ...
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Table 29-6. Port F - Alternate functions PORT F PIN # INTERRUPT TCF0 GND 43 VCC 44 PF0 45 SYNC OC0A PF1 46 SYNC OC0B PF2 47 SYNC/ASYNC OC0C PF3 48 SYNC OC0D PF4 49 SYNC PF5 50 SYNC PF6 ...
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Table 29-9. Port K - Alternate functions PORT K PIN # INTERRUPT GND 73 VCC 74 PK0 75 SYNC Pk1 76 SYNC PK2 77 SYNC/ASYNC PK3 78 SYNC PK4 79 SYNC PK5 80 SYNC PK6 81 SYNC PK7 82 SYNC ...
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Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA A1. For complete register description and summary for each peripheral module, refer to the XMEGA A Manual. Base Address 0x0000 0x0010 ...
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Base Address 0x0A40 0x0A80 0x0A90 0x0AA0 0x0AB0 0x0AC0 0x0B00 0x0B40 0x0B90 0x0BA0 0x0BB0 0x0BC0 8067D–AVR–08/08 Name Description TCE1 Timer/Counter 1 on port E AWEXE Advanced Waveform Extension on port E HIRESE High Resolution Extension on port E USARTE0 USART 0 ...
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Interrupt Vector Summary. 31.1 USART Interrupt vectors Table 31-1. USART Interrupt vectors Offset Source 0 RXC 2 DRE 4 TXC 31.2 Timer/Counter Interrupt vectors Table 31-2. Interrupt vectors Timer/Counter Offset Source 0 OVF 2 ERR 4 CCA 6 CCB ...
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DMA Interrupt vectors Table 31-5. DMA Interrupt vectors Offset Source 0 CH0 2 CH1 4 CH2 6 CH3 31.6 Crystal Oscillator Failure Interrupt vector Table 31-6. Crystal Oscillator Failure Interrupt vector Offset Source 0 OSCF 31.7 RTC Interrupt vectors ...
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Analog Comparator Interrupt vectors Table 31-10. Analog Comparator Interrupt vectors Offset Source 0 COMP0 2 COMP1 4 WINDOW 31.11 ADC Interrupt vectors Table 31-11. Analog to Digital Converter Interrupt vectors Offset Source 0 CH0 2 CH1 4 CH2 6 ...
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Instruction Set Summary Mnemonics Operands Description ADD Rd, Rr Add without Carry ADC Rd, Rr Add with Carry ADIW Rd, K Add Immediate to Word SUB Rd, Rr Subtract without Carry SUBI Rd, K Subtract Immediate SBC Rd, Rr ...
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Mnemonics Operands Description CALL k call Subroutine RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate SBRC Rr, b Skip if Bit in Register ...
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Mnemonics Operands Description LD Rd, -Y Load Indirect and Pre-Decrement LDD Rd, Y+q Load Indirect with Displacement LD Rd, Z Load Indirect LD Rd, Z+ Load Indirect and Post-Increment LD Rd, -Z Load Indirect and Pre-Decrement LDD Rd, Z+q Load ...
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Mnemonics Operands Description ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear SBI A, b Set Bit in I/O Register ...
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Packaging information 33.1 100A PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions ...
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D e 0.90 TYP 10 A 0.90 TYP 2325 Orchard Parkway San Jose, CA 95131 R 8067D–AVR–08/08 E Marked A1 Identifier TOP VIEW Øb A1 Corner 9 8 ...
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Electrical Characteristics - TBD 34.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin with respect to Ground..-0. Maximum Operating Voltage ............................................ 3.6V DC Current per I/O Pin ...
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T = -40°C to 85° 1.6V to 3.6V (unless otherwise noted Symbol Parameter Power Supply Current I CC Power-down mode Power-save mode Note: 1. “Max” means the highest value where the pin is guaranteed to be ...
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Speed The maximum frequency of the XMEGA A1 devices is depending on V 34-1 on page 67 Figure 34-1. Maximum Frequency vs. Vcc 8067D–AVR–08/08 the Frequency vs. V curve is linear between 1.8V < MHz 32 Safe ...
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ADC Characteristics – TBD Table 34-1. ADC Characteristics Symbol Parameter Resolution Integral Non-Linearity (INL) Differential Non-Linearity (DNL) Gain Error Offset Error Conversion Time ADC Clock Frequency AVCC DC Supply Voltage Source Impedance Start-up time AVCC Analog Supply Voltage Table ...
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Table 34-2. ADC Gain Stage Characteristics (Continued) Symbol Parameter Gain Error Signal-to-Noise Ratio (SNR) 8067D–AVR–08/08 Condition AREF = Int. 1.0V 1X Gain, VCC = 3.3V AREF = Ext. 2.5V AREF = Int. 1.0V 2X Gain, VCC = 3.3V AREF = ...
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Table 34-2. ADC Gain Stage Characteristics (Continued) Symbol Parameter Signal Range DC Supply Current Start-up time 34.5 DAC Characteristics – TBD Table 34-3. DAC Characteristics Symbol Parameter Resolution Integral Non-Linearity (INL) Differential Non-Linearity (DNL) Gain Error Offset Error Calibrated Gain/Offset ...
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Table 34-4. Analog Comparator Characteristics Symbol Parameter Current Consumption Start-up time 8067D–AVR–08/08 Condition High Speed mode Low power mode XMEGA A1 Min Typ Max TBD TBD TBD Units µA µs 71 ...
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Typical Characteristics - TBD 8067D–AVR–08/08 XMEGA A1 72 ...
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Errata 36.1 ATxmega128A1 rev Bootloader Section in Flash is non-functional The Bootloader Section is non-functional, and bootloader or application code cannot reside in this part of the Flash. Problem fix/Workaround None, do not use the Bootloader Section. ...
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The ADC has up to ±2 LSB inaccuracy The ADC will have up to ±2 LSB inaccuracy, visible as a saw-tooth pattern on the input volt- age/ output value transfer function of the ADC. The inaccuracy increases with increasing ...
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Datasheet Revision History 37.1 8067D – 08/ 37.2 8067C – 06/ 37.3 8067B – 05/ 10. 11. 12. 13. 8067D–AVR–08/08 ...
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... Inserted a new Figure 15-1 on page 31. Updated Speed grades in “Speed” on page Added a new ATxmega384A1 device in page 2 and “Memories” on page 9. Replaced the Figure 3-1 on page new XMEGA A1 detailed block diagram. Inserted Errata “ATxmega128A1 rev. G” on page Initial revision. ...
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Table of Contents Features ..................................................................................................... 1 Typical Applications ................................................................................ 1 1 Ordering Information ............................................................................... 2 2 Pinout/Block Diagram .............................................................................. 2 3 Overview ................................................................................................... 4 3.1 Block Diagram ...................................................................................................5 4 Resources ................................................................................................. 6 4.1 Recommended reading .....................................................................................6 5 Disclaimer ................................................................................................. 6 ...
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Overview ..........................................................................................................18 10.3 Clock Options ..................................................................................................19 11 Power Management and Sleep Modes ................................................. 21 11.1 Features ..........................................................................................................21 11.2 Overview ..........................................................................................................21 11.3 Sleep Modes ....................................................................................................21 12 System Control and Reset .................................................................... 22 12.1 Features ..........................................................................................................22 12.2 Resetting the AVR ...........................................................................................22 ...
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Overview ..........................................................................................................34 19 TWI - Two-Wire Interface ....................................................................... 35 19.1 Features ..........................................................................................................35 19.2 Overview ..........................................................................................................35 20 SPI - Serial Peripheral Interface ............................................................ 36 20.1 Features ..........................................................................................................36 20.2 Overview ..........................................................................................................36 21 USART ..................................................................................................... 37 21.1 Features ..........................................................................................................37 21.2 Overview ..........................................................................................................37 ...
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JTAG interface .................................................................................................47 28.4 PDI - Program and Debug Interface ................................................................47 29 Pinout and Pin Functions ...................................................................... 48 29.1 Alternate Pin Function Description ..................................................................48 29.2 Alternate Pin Functions ...................................................................................50 30 Peripheral Module Address Map .......................................................... 54 31 Interrupt Vector ...
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Datasheet Revision History ................................................................... 75 37.1 8067D – 08/08 .................................................................................................75 37.2 8067C – 06/08 .................................................................................................75 37.3 8067B – 05/08 .................................................................................................75 37.4 8067A – 02/08 .................................................................................................76 Table of Contents....................................................................................... i ...
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Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to ...