HI-8010J-85 HOLTIC [Holt Integrated Circuits], HI-8010J-85 Datasheet - Page 2

• Manufacturer Part Number: HI-8010J-85
• Description: CMOS HIGH VOLTAGE DISPLAY DRIVER
• Manufacturer: HOLTIC [Holt Integrated Circuits]

FUNCTIONAL DESCRIPTION
Whenever a Logic "0" is applied to the Chip Select (
input, one bit of data is clocked into the shift register from the
serial data input (DIN) with each negative transition of the
Clock (
versions. A Logic "1" present at the Load (LD) input will
cause a parallel transfer of data from the shift register to the
data latch. If the Load (LD) input is held high while data is
clocked into the shift register, the latch will be transparent.
All four logic inputs are TTL compatible on the HI-8010 and
CMOS compatible on the HI-8110.
To display segments, a Logic "1" is stored in the appropriate
shift register bit position, and the segment output is out-of-
phase with the backplane.
The backplane output functions in 1 of 2 modes; externally
driven or self-oscillating. When the LCDØ input is externally
driven with the LCDØOPT input open circuit (Figure 2), the
backplane output will be in-phase with LCDØ. Utilizing the
self-oscillating mode, inputs LCDØ and LCDØOPT are tied
together and connected to an RC circuit (Figure 3).
A 150K
approximate backplane frequency of 100Hz. The
LCDØ/LCDØOPT oscillator frequency is divided by 256 to
determine the backplane output frequency. The resistor
value (R) must be at least 30K
operation.
For displays having a number of segments greater than 38,
two or more of the display drivers may be cascaded together
by connecting the serial data output (DOUT) from the first
driver, to the serial data input (DIN) of the following driver,
etc. (See Figures 2 & 3). Data out (DOUT) will change state
TIMING DIAGRAM
OUTPUT
INPUT
INPUT
INPUT
INPUT
DOUT
DIN
CS
CL
LD
CL
W
) input.
resistor with a 470pF capacitor generates an
CS
is internally tied to VSS on some
t
CSS
t
DS
W
VALID
for proper self-oscillator
t
DH
t
CSH
HI-8010/HI-8110 Series
HOLT INTEGRATED CIRCUITS
CS
)
LCDØ
LCDØ
3-4
OPT
t
INTERNAL OSCILLATOR CIRCUIT
CDO
t
CL
on the rising edge of the Clock (
and Chip Select (
other, respectively, between all cascaded display drivers.
t
VALID
LS
CS
) should be tied in common with each
Figure 1
t
CL
CSL
t
t
LCS
LW
). Clock (
TO BACKPLANE
TRANSLATOR
AND DRIVER
CL
÷ 256
), Load (LD)
Q