74HCT147D,652 NXP Semiconductors, 74HCT147D,652 Datasheet - Page 13
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74HCT147D,652
Manufacturer Part Number
74HCT147D,652
Description
IC 10-4 PRIORITY ENCODER 16-SOIC
Manufacturer
NXP Semiconductors
Series
74HCTr
Type
Priority Encoderr
Datasheets
1.74HCT4046ADB112.pdf
(19 pages)
2.74HCT4046ADB112.pdf
(23 pages)
3.74HC147D653.pdf
(7 pages)
Specifications of 74HCT147D,652
Package / Case
16-SOIC (3.9mm Width)
Circuit
1 x 10:4
Independent Circuits
1
Voltage Supply Source
Single Supply
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Product
Decoders, Encoders, Multiplexers & Demultiplexers
Logic Family
74HCT
Number Of Lines (input / Output)
9.0 / 4.0
Propagation Delay Time
17 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Input Lines
9.0
Number Of Output Lines
4.0
Power Dissipation
500 mW
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output High, Low
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-2777-5
933714980652
933714980652
Philips Semiconductors
AC waveforms 74HCT
Test circuit for 74HCT
March 1988
handbook, full pagewidth
HCMOS family characteristics
C
R
(1) In Fig.9 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals
(2) For AC measurements: t
Fig.9
L
T
(SET, RESET and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual
active levels of the forcing signals are specified in the individual device data sheet.
=
=
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
load capacitance including jig and probe capacitance (see AC
CHARACTERISTICS for values).
termination resistance should be equal to the output impedance Z
the pulse generator.
OUTPUT
PRESET
CLOCK
RESET,
r
INPUT
INPUT
INPUT
DATA
SET,
= t
f
= 6 ns; when measuring f
handbook, halfpage
GENERATOR
10%
1.3 V
PULSE
t su
t rem
1.3 V
t r
10%
1.3 V
t PLH
90%
t WH
max
Fig.10 Test circuit.
1.3 V
V I
90%
t h
, there is no constraint on t
1/f max
t TLH
t f
R T
13
t WL
o
D.U.T
V CC
t su
of
t PHL
V O
r
, t
f
with 50% duty factor.
C L
t h
FAMILY SPECIFICATIONS
t THL
MGK565
50 pF
MGK568
3 V
GND
3 V
GND
3 V
GND