74AHC138D,112 NXP Semiconductors, 74AHC138D,112 Datasheet

IC 3:8 LINE DECOD/DEMUX 16SOIC

74AHC138D,112

Manufacturer Part Number
74AHC138D,112
Description
IC 3:8 LINE DECOD/DEMUX 16SOIC
Manufacturer
NXP Semiconductors
Series
74AHCr
Type
Decoder/Demultiplexerr
Datasheet

Specifications of 74AHC138D,112

Circuit
1 x 3:8
Independent Circuits
1
Current - Output High, Low
8mA, 8mA
Voltage Supply Source
Single Supply
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74AHC138D
74AHC138D
935262999112
1. General description
2. Features
The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin
compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC138; 74AHCT138 is a 3-to-8 line decoder/demultiplexer. It accepts three
binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight
mutually exclusive outputs (Y0 to Y7) that are LOW when selected.
There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3).
Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four 74AHC138; 74AHCT138 devices and one
inverter. The 74AHC138; 74AHCT138 can be used as an eight output demultiplexer by
using one of the active LOW enable inputs as the data input and the remaining enable
inputs as strobes. Unused enable inputs must be permanently tied to their appropriate
active HIGH or LOW state.
74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer; inverting
Rev. 03 — 28 November 2007
Balanced propagation delays
All inputs have Schmitt-trigger action
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Inputs accepts voltages higher than V
For 74AHC138 only: operates with CMOS input levels
For 74AHCT138 only: operates with TTL input levels
ESD protection:
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
CC
Product data sheet

Related parts for 74AHC138D,112

74AHC138D,112 Summary of contents

Page 1

Rev. 03 — 28 November 2007 1. General description The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AHC138D +125 C 74AHCT138D 74AHC138PW +125 C 74AHCT138PW 74AHC138BQ +125 C 74AHCT138BQ 4. Functional diagram Fig 1. Logic symbol Fig 3. Functional diagram 74AHC_AHCT138_3 Product data sheet 74AHC138; 74AHCT138 Description SO16 plastic small outline package; 16 leads; ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning 138 GND 001aad033 Fig 4. Pin configuration for SO16 and TSSOP16 5.2 Pin description Table 2. Pin description Symbol Pin GND 15, 14, 13, 12, 11, 10 74AHC_AHCT138_3 Product data sheet 74AHC138; 74AHCT138 3-to-8 line decoder/demultiplexer; inverting (1) The die substrate is attached to this pad using conductive die attach material ...

Page 4

... NXP Semiconductors 6. Functional description [1] Table 3. Function table Input [ HIGH voltage level LOW voltage level don’t care 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage ...

Page 5

... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V) ...

Page 6

... NXP Semiconductors Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions For type 74AHCT138 V HIGH-level input voltage V LOW-level input voltage V HIGH-level output voltage 8 LOW-level output voltage 8 input leakage GND current 5 supply current 5 additional per input pin; ...

Page 7

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions For type 74AHC138 t propagation An to Yn; see pd delay Yn; see Yn; see power pF dissipation V = GND capacitance 74AHC_AHCT138_3 Product data sheet 74AHC138 ...

Page 8

... NXP Semiconductors Table 7. Dynamic characteristics GND = 0 V; For test circuit see Figure Symbol Parameter Conditions For type 74AHCT138 t propagation An to Yn; see pd delay Yn; see Yn; see power pF dissipation V = GND capacitance [1] Typical values are measured at nominal supply voltage (V [2] ...

Page 9

... NXP Semiconductors Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 7. The inputs En to outputs Yn propagation delays Table 8. Measurement points Type 74AHC138 74AHCT138 74AHC_AHCT138_3 Product data sheet 74AHC138; 74AHCT138 V CC E1, E2 input ...

Page 10

... NXP Semiconductors PULSE GENERATOR Test data is given in Table 9. Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistance Test selection switch. Fig 8. Load circuit for switching times Table 9. Test data Type Input ...

Page 11

... NXP Semiconductors 12. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 12

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 13

... NXP Semiconductors DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 14

... Document ID Release date 74AHC_AHCT138_3 20071128 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section • Section • ...

Page 15

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 16

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 Revision history ...

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