SY89841UMG TR Micrel Inc, SY89841UMG TR Datasheet - Page 10

• Manufacturer Part Number: SY89841UMG TR
• Description: IC MUX 2:1 LVDS RPE 16-MLF
• Manufacturer: Micrel Inc
• Series: SY89r
• Type: Multiplexerr

Specifications of SY89841UMG TR

• Circuit: 1 x 2:1
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-MLF®, QFN
• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.625V
• Package Type: MLF
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: CML/LVDS/PECL
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / Rohs Status: Compliant
• Other names: SY89841UMGTR; SY89841UMGTR

Micrel, Inc.
Case #4: Input Clock Failure: Switching from the
selected clock input stuck in an undetermined state
to a valid clock input (RPE enabled).
If CLK1 fails to an undetermined state (e.g.,
amplitude falls below the 100mV (V
single-ended input limit, or 200mV differentially)
before the RPE MUX selects CLK2 (using the SEL
pin), the switchover to the valid clock CLK2 will
occur either following Case #2 or Case #3,
depending upon the last valid state at the CLK1
Power-On Reset (POR) Description
The SY89841U includes an internal power-on reset
(POR) function to ensure the RPE logic starts-up in
a known logic state once the power-supply voltage is
stable. An external capacitor connected between V
and the CAP pin (pin 11) controls the delay for the
power-on reset function.
The required capacitor value calculation is based
upon the time the system power supply needs to
power up to a minimum of 2.3V. The time constant
for the internal power-on-reset must be greater than
the time required for the power supply to ramp up to
a minimum of 2.3V.
February 2005
OUTPUT
CLK1
CLK2
SEL
Select CLK1
as in case #2
as in case #3
IN
) minimum
CC
Timing Diagram 4
10
If the selected input clock fails to a floating, static, or
extremely low signal swing, including 0mV, the FSI
function will eliminate any metastable condition and
guarantee a stable output signal. No ringing and no
undetermined state will occur at the output under
these conditions.
Please note that the FSI function will not prevent
duty cycle distortions or runt pulses in case of a
slowly deteriorating (but still toggling) input signal.
Due to the FSI function, the propagation delay will
depend on rise and fall time of the input signal and
on its amplitude. Refer to “Typical Operating
Characteristics” for detailed information.
The following formula describes this relationship:
As an example, if the time required for the system
power supply to power up past 2.3V is 12ms, then
the required capacitor value on pin 11 would be:
Select CLK2
C( F)
C( F)
C 1 F
µ
≥ µ
µ
≥
≥
12(ms/ F)
12(ms/ F)
t
dPS
12ms
[e-mail]
(ms)
µ
µ
or [phone]
M9999-021405
SY89841U