CY27C256-150JC Cypress Semiconductor Corporation., CY27C256-150JC Datasheet
CY27C256-150JC
Manufacturer Part Number
CY27C256-150JC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheets
1.CY27C256-150JC.pdf
(11 pages)
2.CY27C256-150JC.pdf
(11 pages)
3.CY27C256-150JC.pdf
(11 pages)
Specifications of CY27C256-150JC
Case
PLCC/32
Date_code
95+
Features
Functional Description
The CY27C256 is a high-performance 32,768-word by 8-bit
CMOS EPROM. When disabled (CE HIGH), the CY27C256
automatically powers down into a low-power stand-by mode.
The CY27C256 is packaged in the industry standard 600-mil
DIP, PLCC, and TSOP packages. The CY27C256 is also avail-
Cypress Semiconductor Corporation
• Wide speed range
• Low power
• Low standby power
•
Note:
1.
— 45 ns to 200 ns (commercial and military)
— 248 mW (commercial)
— 303 mW (military)
— Less than 83 mW when deselected
10% Power supply tolerance
For PLCC only: Pins 1 and 17 are common and tied to the die attach pad. They must therefore be DU (don’t use) for the PLCC package.
Logic Block Diagram
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDRESS
ADDRESS
DECODER
ADDRESS
COLUMN
ROW
CE
OE
PROGRAMABLE
256 x 1024
ARRAY
POWER–DOWN
MULTIPLEXER
8 x 1 OF 128
•
3901 North First Street
27c256–1
able in a CerDIP package equipped with an erasure window
to provide for reprogrammability. When exposed to UV light,
the EPROM is erased and can be reprogrammed. The mem-
ory cells utilize proven EPROM floating gate technology and
byte-wide intelligent programming algorithms.
The CY27C256 offers the advantage of lower power and su-
perior performance and programming yield. The EPROM cell
requires only 12.5V for the super voltage, and low current re-
quirements allow for gang programming. The EPROM cells
allow each memory location to be tested 100% because each
location is written into, erased, and repeatedly exercised prior
to encapsulation. Each EPROM is also tested for AC perfor-
mance to guarantee that after customer programming, the
product will meet both DC and AC specification limits.
Reading the CY27C256 is accomplished by placing active
LOW signals on OE and CE. The contents of the memory location
addressed by the address lines (A
the output lines (O
O
O
O
O
O
O
O
O
7
6
5
4
3
2
1
0
Pin Configurations
32K x 8-Bit CMOS EPROM
•
GND
V
A
O
O
O
PP
A
A
A
A
A
A
A
A
12
7
5
4
3
2
1
0
0
1
2
6
San Jose
DIP/Flatpack
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
27C256
- O
7
).
28
27
26
25
24
23
22
21
20
19
18
17
16
15
27c256–2
•
V
A
A
A
A
A
OE
A
CE
O
O
O
O
O
CC
14
13
8
9
11
10
May 1993 – Revised August 1994
7
6
5
4
3
CA 95134
0
- A
NC
A
A
A
A
A
A
A
O
6
3
2
1
0
5
4
0
14
) will become available on
5
6
7
8
9
10
11
12
13
14151617
LCC/PLCC
4
3 2 1
CY27C256
27C256
•
fax id: 3013
32
181920
408-943-2600
31
[1]
30
29
28
27
26
25
24
23
22
21
27c256–3
A
A
A
NC
OE
A
CE
O
O
8
9
11
10
7
6
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