A3PN125-VQG100 Actel, A3PN125-VQG100 Datasheet

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A3PN125-VQG100

Manufacturer Part Number
A3PN125-VQG100
Description
VQ100/PROASIC3 NANO DEVICES, 1.5 V CORE FOR LOW POWER, 125K SYSTEM GATES
Manufacturer
Actel
Datasheet

Specifications of A3PN125-VQG100

Lead_time
42
Pack_quantity
90
Comm_code
85423990

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A3PN125-VQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3PN125-VQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
January 2010
© 2010 Actel Corporation
ProASIC
Features and Benefits
Wide Range of Features
Reprogrammable Flash Technology
High Performance
In-System Programming (ISP) and Security
Low Power
High-Performance Routing Hierarchy
Table 1 • ProASIC3 nano Devices
ProASIC3 nano Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals
I/O Banks
Maximum User I/Os (packaged device)
Maximum User I/Os (Known Good Die)
Package Pins
Notes:
1. A3PN030 is available in the Z feature grade only.
2. A3PN030 and smaller devices do not support this feature.
3. For higher densities and support of additional features, refer to the
• 10 k to 250 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 71 User I/Os
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
• 350 MHz System Performance
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
• FlashLock
• Low-Power ProASIC3 nano Products
• 1.5 V Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
• Segmented, Hierarchical Routing and Clock Structure
QFN
VQFP
† A3PN030 and smaller devices do not support this feature.
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
®
to Secure FPGA Contents
2
2
®
3 nano Flash FPGAs
2
2
A3PN010
QN48
10 k
260
1 k
86
34
34
4
2
A3PN015
QN68
15 k
128
384
1 k
49
4
3
Advanced I/Os
Clock Conditioning Circuit (CCC) and PLL
Embedded Memory
Enhanced Commercial Temperature Range
A3PN020
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended
• Wide Range Power Supply Voltage Support per JESD8-B,
• I/O Registers on Input, Output, and Enable Paths
• Selectable Schmitt Trigger Inputs
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
• Up to Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
• True Dual-Port SRAM (except ×18 organization)
• –20°C to +70°C
QN68
20 k
172
520
1 k
ProASIC3
2.5 V / 1.8 V / 1.5 V
Allowing I/Os to Operate from 2.7 V to 3.6 V
Capabilities and External Feedback
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
49
52
4
3
and
QN48, QN68
A3PN030
VQ100
30 k
256
768
ProASIC3E
1 k
77
83
6
2
I/O
1
Standards:
A3PN060
handbooks.
VQ100
1,536
60 k
512
Yes
1 k
18
18
71
71
4
1
2
LVTTL,
and Drive Strength
A3PN125
VQ100
125 k
1,024
3,072
Yes
Advance v0.6
1 k
36
18
71
71
8
1
2
LVCMOS
A3PN250
VQ100
250 k
2,048
6,144
Yes
1 k
36
18
68
68
8
1
4
3.3 V /
®
I

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