AGLP125V2-CSG289I Actel, AGLP125V2-CSG289I Datasheet

AGLP125V2-CSG289I

Manufacturer Part Number

AGLP125V2-CSG289I

Description

BGA 289/IC,FPGA,3120-CELL,CMOS

Manufacturer

Actel

Datasheets

1.AGLP125V2-CSG289I.pdf (14 pages)

2.AGLP125V2-CSG289I.pdf (14 pages)

Specifications of AGLP125V2-CSG289I

Lead_time

Pack_quantity

152

Comm_code

85423990

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December 2008

IGLOO PLUS Low-Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

Feature Rich

Reprogrammable Flash Technology

In-System Programming (ISP) and Security

Table 1-1 • IGLOO PLUS Product Family

IGLOO PLUS Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

Secure (AES) ISP

FlashROM Bits

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

Notes:

1. AGLP060 in CS201 does not support the PLL.

2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.

• 1.2 V to 1.5 V Core Voltage Support for Low Power

• Supports Single-Voltage System Operation

• 5 µW Power Consumption in Flash*Freeze Mode

• Low-Power Active FPGA Operation

• Flash*Freeze

• Configurable Hold Previous State, Tristate, HIGH, or LOW

• Easy Entry To / Exit From Ultra-Low-Power Flash*Freeze Mode

• 30 k to 125 k System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 212 User I/Os

• 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design When Powered Off

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

• FlashLock

† The AGLP030 device does not support this feature.

Consumption while Maintaining FPGA Content

State per I/O in Flash*Freeze Mode

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

to Secure FPGA Contents

Technology

Enables

Ultra-Low

Power

†

CS201, CS289

AGLP030

VQ128

High-Performance Routing Hierarchy

Advanced I/O

Clock Conditioning Circuit (CCC) and PLL

Embedded Memory

30 k

256

792

120

1 k

• Segmented, Hierarchical Routing and Clock Structure

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—4 Banks per Chip on All

• Single-Ended

• Selectable Schmitt Trigger Inputs

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Small-Footprint Packages across the IGLOO

• Six CCC Blocks, One with an Integrated PLL

• Configurable

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

• True Dual-Port SRAM (except ×18)

–

IGLOO

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V

PLUS Family

Capabilities, and External Feedback

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

PLUS Devices

CS201, CS289

Phase

I/O

AGLP060

VQ176

1,584

60 k

512

Yes

157

1 k

Standards:

Shift,

†

Multiply/Divide,

LVTTL,

CS281, CS289

AGLP125

†

125 k

1,024

3,120

212

Yes

1 k

†

LVCMOS

v1.3

Delay

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