M1AFS250-FGG256 Actel, M1AFS250-FGG256 Datasheet

M1AFS250-FGG256

Manufacturer Part Number

M1AFS250-FGG256

Description

BGA 256/IC,FPGA,6144-CELL,CMOS

Manufacturer

Actel

Datasheet

1.M1AFS250-FGG256.pdf (330 pages)

Specifications of M1AFS250-FGG256

Lead_time

Pack_quantity

Comm_code

85423990

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

M1AFS250-FGG256

Manufacturer:

Microsemi SoC

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

M1AFS250-FGG256I

Manufacturer:

Microsemi SoC

Quantity:

10 000

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July 2009

Actel Fusion Family of Mixed Signal FPGAs

Features and Benefits

High-Performance Reprogrammable Flash Technology

Embedded Flash Memory

Integrated A/D Converter (ADC) and Analog I/O

On-Chip Clocking Support

Low Power Consumption

Table 1 • Fusion Family

Fusion Devices

ARM Cortex-M1

Pigeon Point Devices

MicroBlade Devices

General

Information

Memory

Analog and I/Os

Note:

• Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Nonvolatile, Retains Program when Powered Off

• Live at Power-Up (LAPU) Single-Chip Solution

• 350 MHz System Performance

• User Flash Memory – 2 Mbits to 8 Mbits

• 1 Kbit of Additional FlashROM

• Up to 12-Bit Resolution and up to 600 Ksps

• Internal 2.56 V or External Reference Voltage

• ADC: Up to 30 Scalable Analog Input Channels

• High-Voltage Input Tolerance: –10.5 V to +12 V

• Current Monitor and Temperature Monitor Blocks

• Up to 10 MOSFET Gate Driver Outputs

• ADC Accuracy is Better than 1%

• Internal 100 MHz RC Oscillator (accurate to 1%)

• Crystal Oscillator Support (32 KHz to 20 MHz)

• Programmable Real-Time Counter (RTC)

• 6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated PLLs

• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

• Sleep and Standby Low-Power Modes

– Configurable 8-, 16-, or 32-Bit Datapath

– 10 ns Access in Read-Ahead Mode

– P- and N-Channel Power MOSFET Support

– Programmable 1, 3, 10, 30 µA, and 20 mA Drive Strengths

– Phase Shift, Multiply/Divide, and Delay Capabilities

– Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz

*Refer to the

Devices

Cortex-M1

System Gates

Tiles (D-flip-flops)

Secure (AES) ISP

PLLs

Globals

Flash Memory Blocks (2 Mbits)

Total Flash Memory Bits

FlashROM Bits

RAM Blocks (4,608 bits)

RAM kbits

Analog Quads

Analog Input Channels

Gate Driver Outputs

I/O Banks (+ JTAG)

Maximum Digital I/Os

Analog I/Os

product brief for more information.

AFS090

90,000

2,304

1,024

Yes

In-System Programming (ISP) and Security

Advanced Digital I/O

SRAMs and FIFOs

Soft ARM

Pigeon Point ATCA IP Support (P1)

MicroBlade Advanced Mezzanine Card Support (U1)

• Secure ISP with 128-Bit AES via JTAG

• FlashLock

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages – Up to 5 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, M-LVDS

• Hot-Swappable I/Os

• Programmable Output Slew Rate, Drive Strength, and Weak

• Pin-Compatible Packages across the Fusion Family

• Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,

• True Dual-Port SRAM (except ×18)

• Programmable Embedded FIFO Control Logic

• ARM Cortex-M1–Enabled (without debug)

• Targeted to Actel's Pigeon Point

• In Partnership with Pigeon Point Systems

• ARM Cortex-M1 Enabled

• Targeted to Advanced Mezzanine Card (AdvancedMC Designs)

• Designed in Partnership with MicroBlade

• 8051-Based Module Management Controller (MMC)

3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

– Built-In I/O Registers

– 700 Mbps DDR Operation

Pull-Up/Down Resistor

and ×18 organizations available)

Reference (BMR) Starter Kits

M1AFS250

AFS250

Cortex™-M1 Fusion Devices (M1)

250,000

6,144

1,024

Yes

114

to Secure FPGA Contents

M1AFS600

P1AFS600

U1AFS600

AFS600

600,000

13,824

1,024

Yes

108

172

Board Management

M1AFS1500

P1AFS1500

1,500,000

Revision 1

AFS1500

38,400

1,024

Yes

270

252

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