SST28SF040A-120-4I-NH Silicon Storage Technology, Inc, SST28SF040A-120-4I-NH Datasheet

SST28SF040A-120-4I-NH

Manufacturer Part Number

SST28SF040A-120-4I-NH

Description

Manufacturer

Silicon Storage Technology, Inc

Datasheets

1.SST28VF040A-200-4C-NH.pdf (26 pages)

2.SST28VF040A-200-4C-NH.pdf (24 pages)

3.SST28SF040A-120-4I-NH.pdf (25 pages)

Specifications of SST28SF040A-120-4I-NH

Case

PLCC

Date_code

05+

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

SST28SF040A-120-4I-NH

Manufacturer:

SST

Quantity:

6 000

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

SST28SF040A-120-4I-NH

Manufacturer:

SST

Quantity:

6 000

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FEATURES:

• Single Voltage Read and Write Operations

• Superior Reliability

• Memory Organization: 512K x8

• Sector-Erase Capability: 256 Bytes per Sector

• Low Power Consumption

• Fast Sector-Erase/Byte-Program Operation

PRODUCT DESCRIPTION

The SST28SF/VF040A are 512K x8 bit CMOS Sector-

Erase, Byte-Program EEPROMs. The SST28SF/VF040A

are manufactured using SST’s proprietary, high perfor-

mance CMOS SuperFlash EEPROM Technology. The

split-gate cell design and thick-oxide tunneling injector

attain better reliability and manufacturability compared with

alternative approaches. The SST28SF/VF040A erase and

program with a single power supply. The SST28SF/

VF040A conform to JEDEC standard pinouts for byte wide

memories and are compatible with existing industry stan-

dard flash EEPROM pinouts.

Featuring high performance programming, the SST28SF/

VF040A typically Byte-Program in 35 µs. The SST28SF/

VF040A typically Sector-Erase in 2 ms. Both Program and

Erase times can be optimized using interface features such

as Toggle bit or Data# Polling to indicate the completion of

the Write cycle. To protect against an inadvertent write, the

SST28SF/VF040A have on chip hardware and Software

Data Protection schemes. Designed, manufactured, and

tested for a wide spectrum of applications, the SST28SF/

VF040A are offered with a guaranteed sector endurance of

10,000 cycles. Data retention is rated greater than 100

years.

The SST28SF/VF040A are best suited for applications that

require re-programmable nonvolatile mass storage of pro-

gram, configuration, or data memory. For all system appli-

S71077-05-000 3/03

– 4.5-5.5V-only for SST28SF040A

– 2.7-3.6V for SST28VF040A

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

– Active Current: 15 mA (typical) for 5.0V and

– Standby Current: 5 µA (typical)

– Byte-Program Time: 35 µs (typical)

– Sector-Erase Time: 2 ms (typical)

– Complete Memory Rewrite: 20 sec (typical)

10 mA (typical) for 2.7-3.6V

4 Mbit (512K x8) SuperFlash EEPROM

310

Byte-Program, Small Erase Sector flash memories

SST28SF040A / SST28VF040A

SST28SF / VF040A4Mb (x8)

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

• Fast Read Access Time

• Latched Address and Data

• Hardware and Software Data Protection

• End-of-Write Detection

• TTL I/O Compatibility

• JEDEC Standard

• Packages Available

cations, the SST28SF/VF040A significantly improve

performance and reliability, while lowering power consump-

tion when compared with floppy diskettes or EPROM

approaches. Flash EEPROM technology makes possible

convenient and economical updating of codes and control

programs on-line. The SST28SF/VF040A improve flexibil-

ity, while lowering the cost of program and configuration

storage application.

The functional block diagram shows the functional blocks of

the SST28SF/VF040A. Figures 1, 2, and 3 show the pin

assignments for the 32-lead PLCC, 32-lead TSOP , and 32-

pin PDIP packages. Pin descriptions and operation modes

are described in Tables 2 through 5.

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asserting WE# low while keeping CE#

low. The address bus is latched on the falling edge of WE#

or CE#, whichever occurs last. The data bus is latched on

the rising edge of WE# or CE#, whichever occurs first.

Note, during the Software Data Protection sequence the

addresses are latched on the rising edge of OE# or CE#,

whichever occurs first.

– 4.5-5.5V-only operation: 90 and 120 ns

– 2.7-3.6V operation: 150 and 200 ns

– 7-Read-Cycle-Sequence Software Data

– Toggle Bit

– Data# Polling

– Flash EEPROM Pinouts

– 32-lead PLCC

– 32-lead TSOP (8mm x 20mm)

– 32-pin PDIP

Protection

These specifications are subject to change without notice.

SSF is a trademark of Silicon Storage Technology, Inc.

Data Sheet

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