AFE8201PFBR BURR-BROWN [Burr-Brown Corporation], AFE8201PFBR Datasheet - Page 8

• Manufacturer Part Number: AFE8201PFBR
• Description: IF Analog-to-Digital Converter with Digital Downconverter
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

AFE8201
SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005
The SPI interface consists of four signals: a serial clock (SCK), an active-low chip select (CS_N), a serial data input
(MOSI—Master Out, Slave In), and a serial data output (MISO—Master In, Slave Out). Data is transferred in groups
of 32 bits. The first 16 bits are the instruction, which indicate:
The second 16 bits is the data transfer, which is input on MOSI for a write cycle or output on MISO for a read cycle.
A single data word write cycle is shown in Figure 4. The cycle is initiated by the high-to-low transition of the CS_N
line. 32 SCK pulses clock the instruction and the data into the MOSI line. Instructions and data are clocked in MSB
first. The first 16 bits are the instruction; the second 16 bits are the data word. There are two possible single data
word write cycle instructions: register write and memory write. The formats for these instructions are shown in
Figure 5 and Figure 6.
The only information required for a register write is the 5-bit register address (REG_ADDR). For a memory write, the
2-bit memory select (MEM) and the 8-bit memory address (MEM_ADDR) are required.
Following the 16-bit instruction, the 16-bit data word is clocked in, again MSB first. At the end of the write cycle this
data word is written to the appropriate register or memory location in the AFE.
8
CS_N
MOSI
MISO
(1) if data is to be written or to be read;
(2) if the data target is a control register or a memory bank; and
(3) the address of the data target.
SCK
Memory Bank Address
15
15
1
1
Figure 4. Single Data Word Control Interface Write Cycle for Registers or Memory
14
14
0
0
0
1
2
MSB
13
13
0
1
12
12
Don’t Care
Instruction
11
11
Figure 5. Register Write Instruction Format
FIR Filter 2A Coefficients
FIR Filter 2B Coefficients
Figure 6. Memory Write Instruction Format
FIR Filter 1 Coefficients
REG_ADDR
Description
10
10
Table 2. Memory Banks
9
9
MEM
8
8
7
7
128 Coefficients
128 Coefficients
64 Coefficients
6
6
Size
5
5
MEM_ADDR
Data
Don’t Care
4
4
3
3
2
2
Data Memory
126 Samples
126 Samples
62 Samples
1
1
LSB
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