AFE8201PFBR BURR-BROWN [Burr-Brown Corporation], AFE8201PFBR Datasheet - Page 9

• Manufacturer Part Number: AFE8201PFBR
• Description: IF Analog-to-Digital Converter with Digital Downconverter
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

The read cycle is illustrated in Figure 7. It is similar to the write cycle, except that instead of the data word being
clocked into MOSI during the second half of the cycle, the data word is clocked out of MISO. The two data read
instructions are similar to the corresponding data write instructions and are shown in Figure 8 and Figure 9.
Block transfers are supported for memory reading and writing. Multiple data words are transmitted following the
memory read or write instruction for a block transfer. The data words are sequentially read from or written to RAM
sequentially starting at the address contained in the instruction. The sequential RAM access terminates when the
CS_N line goes high. Figure 10 shows a memory block read cycle. In the illustration, three successive memory
locations are read starting at address N. The memory block write cycle is similar, except of course data is clocked
into MOSI.
In all cases, the control interface is reset when CS_N goes high. If the final SCK is not received before CS_N goes
high, then the cycle will end prematurely. For a read cycle, transfer of data will terminate; for a write cycle, no data
will be written to register or memory.
CS_N
MISO
SCK
CS_N
MOSI
MISO
SCK
www.ti.com
15
15
0
0
MSB
Figure 7. Single Data Word Control Interface Read Cycle for Registers or Memory
14
14
1
1
MSB
Instruction
13
13
0
1
12
12
Figure 10. Block Memory Read Cycle Control Interface
Don’t Care
Instruction
LSB
11
11
MSB
Figure 8. Register Read Instruction Format
Figure 9. Memory Read Instruction Format
REG_ADDR
10
10
Data (N)
9
9
MEM
8
8
MSB
LSB
7
7
Data (N + 1)
6
6
SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005
5
5
MEM_ADDR
Don’t Care
4
4
Data
3
3
Data (N + 2)
2
2
1
1
LSB
AFE8201
LSB
0
0
9