HI-303/883 INTERSIL [Intersil Corporation], HI-303/883 Datasheet

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HI-303/883

Manufacturer Part Number
HI-303/883
Description
Dual SPDT CMOS Analog Switch
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
Dual SPDT CMOS Analog Switch
The HI-303/883 switch is a monolithic device fabricated
using CMOS technology and the Intersil Dielectric Isolation
process. This switch features break-before-make switching,
low and nearly constant ON resistance over the full analog
signal range, and low power dissipation.
The HI-303/883 is TTL compatible and has a logic “0”
condition with an input less than 0.8V and a logic “1”
condition with an input greater than 4.0V.
The HI-303/883 is pin-for-pin compatible with the industry
standard Siliconix DG303. The device is available in a 14 pin
Ceramic DIP. The HI-303/883 operates over the -55°C to
+125°C temperature range.
Pinout
LOGIC
0
1
GND
NC
S
D
D
S
A
3
3
1
1
1
HI1-303/883 (CERAMIC DIP)
1
2
3
4
5
6
7
TOP VIEW
®
SW1
SW2
Off
On
1
Data Sheet
14
13
12
11
10
9
8
V+
S
D
D
S
A
V-
4
2
4
2
2
SW3
SW4
On
Off
1-888-INTERSIL or 321-724-7143
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• This Circuit is Processed in Accordance to MIL-STD-883
• Analog Signal Range (±15V Supplies). . . . . . . . . . . .±15V
• Low Leakage (+25°C) . . . . . . . . . . . . . . . . . . . .1nA (Max)
• Low Leakage (+125°C) . . . . . . . . . . . . . . . . .100nA (Max)
• Low ON Resistance . . . . . . . . . . . . . . . . . . . . . 50Ω (Max)
• Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . 30pC (Typ)
• TTL Compatible
• System Switch Elements
• Low Operating Power
• Compatible with DG303
Applications
• Sample and Hold, i.e. Low Leakage Switching
• Op Amp Gain Switching, i.e. Low ON Resistance
• Portable, Battery Operated Circuits
• Low Level Switching Circuits
• Dual or Single Supply Systems
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
November 2003
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
HI-303/883
FN6058

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HI-303/883 Summary of contents

Page 1

... This switch features break-before-make switching, low and nearly constant ON resistance over the full analog signal range, and low power dissipation. The HI-303/883 is TTL compatible and has a logic “0” condition with an input less than 0.8V and a logic “1” condition with an input greater than 4.0V. ...

Page 2

... Input Current Supply Current +I All Channels Supply Current -I All Channels HI-303/883 Thermal Information Thermal Resistance CERDIP Package +1.5V SUPPLY Package Power Dissipation at 75 -1.5V Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . 0.85W/ SUPPLY +4V Package Power Dissipation Derating Factor above +75 SUPPLY -4V Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . 11.36mW/ ...

Page 3

... TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-in) Final Electrical Test Parameters Group A Test Requirements Groups C & D Endpoints NOTE: 2. PDA applies to Subgroup 1 only. 3 HI-303/883 = −15V, GND = 0V, Unless Otherwise Specified. GROUP A SUB- CONDITIONS GROUPS C = 33pF 300Ω ...

Page 4

... CC GND FIGURE 1. INPUT LEAKAGE CURRENT GND FIGURE (OFF GND FIGURE 5. SUPPLY CURRENTS 4 HI-303/883 + (DRIVER CTE NOTE GND FIGURE 2 ...

Page 5

... GND FIGURE Test Waveforms +15V + LOGIC INPUT V- -15V GND FIGURE 10. 5 HI-303/883 GEN 1kΩ FIGURE 9. CROSSTALK BETWEEN CHANNELS SWITCH V = +3V S2 OUTPUT LOGIC INPUT D S FIGURE 8. OFF CHANNEL ISOLATION ...

Page 6

... GND 8 -V HI-303/883 CERAMIC DIP LOGIC “1” = SWITCH ON V INH 0V 50 OPEN FIGURE 13. TTL LOGIC INPUT + 50% OUT 1 OUT 2 ...

Page 7

... Schematic Diagram V+ D2A MP1A 200Ω LOGIC IN D1A MN1A GND V- FIGURE 14. DIGITAL INPUT BUFFER AND LEVEL SHIFTER HI-303/883 MP2A MP3A MP4A MN2A MN3A MN4A V+ MN1B MN2B MN3B MP5B MP4B MN4B MP3B MP2B MP1B FIGURE 15. SWITCH CELL MP5A MP6A MP7A ...

Page 8

... NOTE: The net leakage into the source or drain is the N-Channel leakage minus the P-Channel leakage. This difference can be positive, negative or zero depending on the analog voltage and temperature, and will vary greatly from unit to unit. 8 HI-303/883 +15V -15V, Unless Otherwise Specified. ...

Page 9

... OFF t BBM 0.2 HI-301/303 ONLY POSITIVE SUPPLY VOLTAGE (V) FIGURE 26. SWITCHING TIME AND BREAK-BEFORE-MAKE TIME vs POSITIVE SUPPLY VOLTAGE 9 HI-303/883 +15V -15V, Unless Otherwise Specified. (Continued FIGURE 23. DIGITAL INPUT CAPACITANCE vs INPUT 300 200 100 65 85 105 125 o C) FIGURE 25. SWITCHING TIME vs NEGATIVE SUPPLY ...

Page 10

... S 10 HI-303/883 DIE ATTACH: Material: Gold/Silicon Eutectic Alloy Temperature: Ceramic DIP - 460°C (Max) WORST CASE CURRENT DENSITY: 3 This device meets Glassivation Integrity Test requirement per MIL-STD-883 Method 2021 and MIL-M-38510 para- graph 3.5.5.4 HI-303/883 ...

Page 11

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 HI-303/883 F14.3 c1 LEAD FINISH ...

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