E4717DBG SEMTECH [Semtech Corporation], E4717DBG Datasheet - Page 7

• Manufacturer Part Number: E4717DBG
• Description: Quad Channel, Per Pin Precision Measurement Unit
• Manufacturer: SEMTECH [Semtech Corporation]

FORCE/SENSE
FORCE is an analog output which either forces a current
or forces a voltage, depending on which operating mode
is selected. In FV mode, the voltage forced is equivalent
to the voltage applied to the VINP pin. In FI mode, the
current forced is mapped to the input as described in the
Force Current section. FORCE can be placed in a high-
impedance state through the setting of the HIZ input pin.
When the HIZ input pin is set to logical “0”, the Edge4717D
FORCE output will be controlled by the internal driver
amplifier, and the Edge4717D will force a user-defined
current or voltage (depending upon the setting of FV/FI*)
at the FORCE pin. When HIZ is set to logical “1”, the
FORCE output is placed into a low-leakage, high impedance
state.
SENSE is a high impedance analog input which measures
the DUT voltage in the MV operating mode.
(FORCE and SENSE are brought out to separate pins to
allow remote sensing.)
IVMON
IVMON is a real time analog voltage output which tracks
the sensed parameter.
In the MV mode (MI/MV* = 0), the output voltage
displayed at IVMON is a 1:1 mapping of the SENSE voltage.
In the MI mode (MI/MV* = 1), IVMON follows the equation:
Using nominal values for the external resistors (RA, RB,
and RC), a voltage at IVMON of +2V corresponds to Imax,
and –2V corresponds to Imin of the selected current range.
For Range D, +1.2V corresponds to Imax and –1.2V
corresponds to Imin.
The IVMON pin can also be placed into a high impedance
state by using the DISABLE input (see Table 3).
TEST AND MEASUREMENT PRODUCTS
Circuit Description (continued)
2005 Semtech Corp. / Rev. 5, 10/14/05
IVMON = I(measured) * REXT
Sample and Hold
The Edge4717D features a sample and hold circuit (per
channel) which can be used to capture the corresponding
voltage value of the sensed parameter (MI or MV) to be
displayed at IVMON.
The output of the sample and hold is internally connected
to IVMON through a latch controlled by LTCH_MODE. The
setting of LTCH_MODE determines whether the data at
IVMON comes from the sample and hold circuit or directly
from the sensed parameter (see Table 4).
Note: No update is performed on the sample-and-hold.
Sample and Hold Testing
An analog MUX in the 4717D allows for testing of the
sample-and-hold circuit.
The MUX control pin, TEST, is a TTL compatible input
whose operation is described in Table 5. To test the sample
and hold circuitry, an analog signal can be applied to the
TEST_IN pin and sampled.
7
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