AT52BC6402A-85CI ATMEL [ATMEL Corporation], AT52BC6402A-85CI Datasheet - Page 32
AT52BC6402A-85CI
Manufacturer Part Number
AT52BC6402A-85CI
Description
64 MBIT FLASH 16 MBIT PSRAM
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT52BC6402A-85CI.pdf
(38 pages)
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Read Cycle 1
Read Cycle 2, CS2 = V
Read Cycle 3, CS2 = V
Notes:
32
1. Read Cycle occurs whenever a high on the PSWE and PSOE is low, while UB and/or LB and CS1 and CS2 are in
2. PSOE = V
3. The t
4. CS1 in high for the standby, low for active.
DATA OUT
DATA OUT
ADDRESS
DATA OUT
ADDRESS
AT52BC6402A(T)
active status.
are defined as the time at which the outputs achieve the low impedance state. These are not referenced to output
voltage levels.
UB, LB
PSOE
CS1
CS2
CS1
CHZ
(1),(4)
, t
IL
BHZ
.
HIGH-Z
and t
V
HIGH-Z
IH
IH
IH
OHZ
(1),(2),(4)
(1),(2),(4)
are defined as the time at which the outputs achieve the high impedance state and t
PREVIOUS DATA
t
OH
t
t
CLZ
CLZ
(3)
t
(3)
AA
t
t
AA
BLZ
t
OLZ
t
t
ACS
ACS
(3)
(3)
t
BA
t
OE
t
RC
t
RC
DATA VALID
DATA VALID
DATA VALID
t
OHZ
t
BHZ
(3)
t
(3)
CHZ
t
CHZ
(3)
t
(3)
OH
t
OH
OLZ
3441B–STKD–11/04
, t
BLZ
and t
CLZ
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