AT52BR1672-85CI ATMEL [ATMEL Corporation], AT52BR1672-85CI Datasheet

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AT52BR1672-85CI

Manufacturer Part Number
AT52BR1672-85CI
Description
16-megabit Flash and 2-megabit/ 4-megabit SRAM Stack Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
Features
Flash
SRAM
Device Number
AT52BR1672(T)
AT52BR1674(T)
16-Mbit Flash and 2-Mbit/4-Mbit SRAM
Single 66-ball 8 mm x 10 mm x 1.2 mm CBGA Package
2.7V to 3.3V Operating Voltage
2.7V to 3.3V Read/Write
Access Time – 85 ns
Sector Erase Architecture
Fast Word Program Time – 20 µs
Fast Sector Erase Time – 300 ms
Dual-plane Organization, Permitting Concurrent Read While Program/Erase
Erase Suspend Capability
Low-power Operation
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
VPP Pin for Accelerated Program/Erase Operations
RESET Input for Device Initialization
Sector Lockdown Support
Top/Bottom Block Configuration
128-bit Protection Register
2-megabit (128K x 16)/4-megabit (256K x 16)
2.7V to 3.3V V
70 ns Access Time
Fully Static Operation and Tri-state Output
1.2V (Min) Data Retention
Industrial Temperature Range
– Thirty-one 32K Word (64K Byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout
– Memory Plane A: Eight 4K Word and Seven 32K Word Sectors
– Memory Plane B: Twenty-four 32K Word Sectors
– Supports Reading and Programming from Any Sector by Suspending Erase of a
– Supports Reading Any Word by Suspending Programming of Any Other Word
– 30 mA Active
– 10 µA Standby
Different Sector
CC
Operating Voltage
Architecture
Flash Plane
12M + 4M
12M + 4M
Configuration
16M (1M x 16)
16M (1M x 16)
Flash
2M (128K x 16)
4M (256K x 16)
Configuration
SRAM
16-megabit
Flash and
2-megabit/
4-megabit
SRAM Stack
Memory
AT52BR1672(T)
AT52BR1674(T)
Preliminary
Rev. 2604B–STKD–09/02
1

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AT52BR1672-85CI Summary of contents

Page 1

... Industrial Temperature Range Flash Plane Device Number Architecture AT52BR1672(T) 12M + 4M AT52BR1674(T) 12M + 4M Flash SRAM Configuration Configuration 16M (1M x 16) 2M (128K x 16) 16M (1M x 16) 4M (256K x 16) 16-megabit Flash and 2-megabit/ 4-megabit SRAM Stack Memory AT52BR1672(T) AT52BR1674(T) Preliminary Rev. 2604B–STKD–09/02 1 ...

Page 2

... CBGA Top View Pin Configurations Pin Name A0 - A16 A0 - A17 A18 - A19 CE OE/SOE WE/SWE VCC VPP I/O0-I/O15 SCS1, SCS2 RDY/BUSY SVCC GND/SGND SUB SLB NC RESET AT52BR1672(T)/1674( A11 A15 A14 B A16 A8 A10 RDY BUSY D SGND RESET ...

Page 3

... Description The AT52BR1672(T) combines a 16-megabit Flash (1M x 16) and a 2-megabit SRAM (orga- nized as 128K x 16 stacked CBGA package; while the AT52BR1674(T) combines a 16- megabit Flash (1M x 16) and a 4-megabit SRAM (organized as 256K x 16 stacked CBGA package. Both devices operate at 2.7V to 3.3V in the industrial temperature range. The mod- ules use a 16-megabit Flash with dual plane architecture for concurrent read/write operations ...

Page 4

... It is not recommended that the six-byte code reside in the software of the final product but only exist in external program- ming code. AT52BR1672(T)/1674( Erase and Erase Suspend/Resume commands will not work while in this mode ...

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... BUFFER INPUT A0 - A19 BUFFER ADDRESS LATCH Y-DECODER X-DECODER 2604B–STKD–09/02 I/O0 - I/O15 INPUT BUFFER IDENTIFIER REGISTER STATUS REGISTER COMMAND REGISTER DATA COMPARATOR WRITE STATE MACHINE Y-GATING PLANE B SECTORS PLANE A SECTORS AT52BR1672(T)/1674( RESET RDY/BUSY PROGRAM/ERASE VPP VOLTAGE SWITCH VCC GND 5 ...

Page 6

... VPP PIN: The circuitry of the 16-megabit Flash is designed so that the device can be pro- grammed or erased from the V than or equal to the VCC pin, the device selects the V AT52BR1672(T)/1674(T) 6 power supply or from the VPP input pin. When V CC supply for programming and erase CC ...

Page 7

... Identification Entry/Exit” on page 21. The manufacturer and device codes are the same for both modes. 2604B–STKD–09/02 input and the V PP signal is used to accelerate program and erase operations, the V AT52BR1672(T)/1674(T) supply, the device will select the V CC power supply in its selection for 2.7V < V ...

Page 8

... CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from OUTPUT LEVELS: For the 16-megabit Flash, output high levels (V 0.2V (not V levels, V minimum power). AT52BR1672(T)/1674( For 2.7V - 3.3V output levels must be regulated to 2.0V ± 10%, while V CCQ sense below 1 ...

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... AA AAA 55 555 90 AA AAA 55 555 AAA 55 555 C0 AA AAA 55 555 C0 AA AAA 55 555 90 *NOTICE: + 0.6V CC AT52BR1672(T)/1674(T) 4th Bus 5th Bus Cycle Cycle Addr Data Addr Data Addr 555 AA AAA 55 555 555 AA AAA 55 SA Addr D IN 555 AA AAA 55 555 555 AA ...

Page 10

... Word Use Block 0 Factory 1 Factory 2 Factory 3 Factory 4 User 5 User 6 User 7 User Note: 1. All address lines not specified in the above table must be 0 when accessing the protection register, i.e., A19 - AT52BR1672(T)/1674( ...

Page 11

... SA27 A SA28 A SA29 A SA30 A SA31 A SA32 A SA33 A SA34 A SA35 A SA36 A SA37 A SA38 2604B–STKD–09/02 AT52BR1672(T)/1674(T) Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K ...

Page 12

... SA24 B SA25 B SA26 B SA27 B SA28 B SA29 B SA30 B SA31 B SA32 B SA33 B SA34 B SA35 B SA36 B SA37 B SA38 AT52BR1672(T)/1674(T) 12 Size (Words 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K ...

Page 13

... A19 = A19 = ≤ 3.3V. For faster erase/program operations AT52BR1672(T)/1674(T) AT52BR1674(T)-85 -40°C - 85°C 2.7V to 3. OUT High-Z High-Z X High-Z ( Manufacturer Code ( ...

Page 14

... Output Low Voltage OL1 V Output Low Voltage OL2 V Output High Voltage OH1 V Output High Voltage OH2 Notes the erase mode mA For 3.3V < V < 3.6V AT52BR1672(T)/1674(T) 14 Condition ...

Page 15

... AT52BR1672(T)-85 Min ADDRESS VALID tCE tOE tACC tRO HIGH Z OUTPUT VALID - t after the address transition without impact on t ACC after the falling edge of CE without impact AT52BR1672(T)/1674(T) AT52BR1674(T)-85 Max Min Max ...

Page 16

... Input Test Waveforms and Measurement Level < Output Test Load Pin Capacitance ( MHz 25°C Symbol Typ OUT Note: 1. This parameter is characterized and is not 100% tested. AT52BR1672(T)/1674(T) 16 Max Units Conditions OUT 2604B–STKD–09/02 ...

Page 17

... Chip Select Hold Time CH t Write Pulse Width ( Data Setup Time Data, OE Hold Time DH OEH t Write Pulse Width High WPH AC Word Load Waveforms WE Controlled CE Controlled 2604B–STKD–09/02 AT52BR1672(T)/1674(T) Min Max Units ...

Page 18

... ECVPP PP t Sector Erase Cycle Time (V SEC PP t Erase or Program Suspend Time EPS Program Cycle Waveforms A19 555 AT52BR1672(T)/1674(T) 18 < 4.5V) PP > 4.5V) < 4.5V) PROGRAM CYCLE WPH t DH 555 AAA Min Typ Max 20 ...

Page 19

... Command Definitions.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H. 2604B–STKD–09/02 t WPH t DH AAA 555 555 WORD 1 WORD 2 WORD 3 AT52BR1672(T)/1674( SR/W ADDRESS AAA Note 2 VALID OUTPUT 55 Note 3 VALID t WORD 4 ...

Page 20

... Toggling either both OE and CE will operate toggle bit. The t specification must be met by the toggling input(s). OEHP 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. AT52BR1672(T)/1674(T) 20 (1) (1) Min Typ Max ...

Page 21

... Sector Lockdown Enable Algorithm (1)(6) LOAD DATA F0 TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION (4) MODE Notes AT52BR1672(T)/1674(T) LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA 80 TO ADDRESS 555 LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA ...

Page 22

... DATA Erase Suspended & Read Erasing Sector Erase Suspended & Read DATA Non-erasing Sector Erase Suspended & I/O7 Program Non-erasing Sector in Plane A Erase Suspended & DATA Program Non-erasing Sector in Plane B AT52BR1672(T)/1674(T) 22 Status Bit I/O7 Plane B Plane A DATA TOGGLE I/O7 DATA 0 DATA TOGGLE 0 DATA ...

Page 23

... Battery Backup – 1.2V (Min) Data Retention Voltage (V) 2.7 - 3.3 Block Diagram SCS1 SCS2 SOE SLB SUB SWE 2604B–STKD–09/02 Operation Current/I Speed (ns) (Max A16 AT52BR1672(T)/1674(T) Standby (mA) Current (µA) Temperature CC (Max - ROW DECODER MEMORY ARRAY 512K X 16 (°C) I/O0 I/O7 I/O8 I/O15 23 ...

Page 24

... Parameter V Supply Voltage CC V Ground SS V Input High Voltage IH (1) V Input Low Voltage IL Note: 1. Undershoot -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested. IL AT52BR1672(T)/1674(T) 24 (1) Rating -0.3 to 3.6 -0.3 to 4.6 - -55 to 150 (2) (2) SLB SUB Mode X X Deselected ...

Page 25

... MHz) Symbol Parameter C Input Capacitance (Add, SCS1, IN SCS2, SLB, SUB, SWE, SOE) C Output Capacitance (I/O) OUT Note: 1. These parameters are sampled and not 100% tested. 2604B–STKD–09/02 AT52BR1672(T)/1674(T) Test Condition V < V < < V < OUT ...

Page 26

... AC Test Conditions TA = -40°C to 85°C, Unless Otherwise Specified Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load TTL Load TTL Load AT52BR1672(T)/1674( Min Max ...

Page 27

... ACS (3) t OLZ t (3) BLZ t (3) CLZ HIGH PREVIOUS DATA t ACS t (3) CLZ AT52BR1672(T)/1674( (3) t CHZ (3) t BHZ t (3) OHZ DATA VALID t OH DATA VALID t (3) CHZ DATA VALID 27 ...

Page 28

... Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested. 8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active. AT52BR1672(T)/1674(T) 28 (1),(4),(8) ...

Page 29

... SCS2 ≤ 0. ≤ V ≤ See Data Retention Timing Diagram = 25°C. Typical values are sampled and not 100% tested. A DATA RETENTION MODE t CDR SCS1 > VCC - 0.2V DATA RETENTION MODE t CDR SCS2 < 0.2V AT52BR1672(T)/1674(T) Min Typ Max 1.2 3.3 9.5 (1) 0.4 0 Unit V µ ...

Page 30

... Fully Static Operation and Tri-state Output • TTL Compatible Inputs and Outputs • Battery Backup – 1.2V (Min) Data Retention Voltage (V) 2.7 - 3.3 Block Diagram SCS1 SCS2 SOE SWE AT52BR1672(T)/1674(T) 30 Operation Current/I Speed (ns) (Max A17 SLB SUB Standby (mA) Current (µA) Temperature ...

Page 31

... Output Disabled Write Read Min 2.7 0 2.2 (1) -0.31 AT52BR1672(T)/1674(T) Unit V V °C °C 1.0 W I/O Pin I/O0 - I/O7 I/O8 - I/O15 High-Z High-Z High-Z High-Z D High-Z IN High High High-Z OUT High-Z D OUT ...

Page 32

... Output High OH (1) Capacitance (Temp = 25° 1.0 MHz) Symbol Parameter C Input Capacitance (Add, SCS1, IN SCS2, SLB, SUB, SWE, SOE) C Output Capacitance (I/O) OUT Note: 1. These parameters are sampled and not 100% tested. AT52BR1672(T)/1674(T) 32 Test Condition V < V < < V < OUT CC ...

Page 33

... TA = -40°C to 85°C, Unless Otherwise Specified Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load TTL Load TTL Load 2604B–STKD–09/02 AT52BR1672(T)/1674( Min Max ...

Page 34

... Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested. 4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the standby, low for active. AT52BR1672(T)/1674( ...

Page 35

... HIGH-Z DATA VALID (3)(7) t WHZ (1),(4),( HIGH-Z HIGH-Z AT52BR1672(T)/1674(T) ( (5) (5) ( DATA VALID 35 ...

Page 36

... Typical values are under the condition read cycle time. RC Data Retention Timing Diagram 1 VCC 2.7V IH VDR SCS1 VSS Data Retention Timing Diagram 2 VCC 2.7V SCS2 VDR 0.4V VSS AT52BR1672(T)/1674(T) 36 Test Condition SCS1 > 0. SCS2 < 0. SUB, SLB > 0. > 0. < ...

Page 37

... Plastic Chip-scale Ball Grid Array Package (CBGA) 2604B–STKD–09/02 AT52BR1672(T)/1674(T) Ordering Code AT52BR1672(T)-85CI AT52BR1674(T)-85CI AT52BR1672-85CI AT52BR1674-85CI Package Type Package Operation Range 66C5 Industrial (-40° to 85°C) 66C5 Industrial (-40° to 85°C) 66C5 Industrial (-40° to 85°C) ...

Page 38

... Øb Bottom View TITLE 2325 Orchard Parkway San Jose, CA 95131 R AT52BR1672(T)/1674( Ball Corner e 1.20 REF 66C5, 66-ball ( Array 1.2 mm Body, 0.8 mm Ball Pitch Chip-scale Ball Grid Array Package (CBGA) ...

Page 39

Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem ...

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