AT52SC1283J-70CI ATMEL [ATMEL Corporation], AT52SC1283J-70CI Datasheet - Page 40

• Manufacturer Part Number: AT52SC1283J-70CI
• Description: 128-Mbit Flash + 32-Mbit/64-Mbit
• Manufacturer: ATMEL [ATMEL Corporation]

38. PSRAM Description
39. PSRAM Features
40. Functional Block Diagram
40
AT52SC1283J/1284J [Preliminary]
The Pseudo-SRAM (PSRAM) is an integrated memory based on a self-refresh DRAM array. It is
designed to be identical in operation and interface to the standard 6T SRAMS. The device is
designed for low standby, low operating current and includes a user configurable low-power
mode. Two chip selects (PCS1 and ZZ) and an output enable (POE) is available to allow for
easy memory expansion. Byte controls (PUB and PLB) allow the upper and lower bytes to be
accessed independently and can also be used to deselect the device. The deep sleep mode
reduces standby current drain while not retaining data in the array.
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Fast Cycle Times
Very Low Standby Current
Very Low Operating Current
Memory Expansion with PCS1 and POE
TTL Compatible Three-state Output Driver
– T
– I
– 1.0 mA at 1 µs (Typical)
SB0
ACC
< 10 µA
< 70 ns
I/O8 ~ I/O15
PCS1
P
P
P
P
WE
UB
Z Z
OE
LB
Addresses
I/O0 ~ I/O7
Row
Control Logic
Clk Gen
Data
Cont
Data
Cont
Data
Cont
Select
Row
Column Addresses
Precharge Circuit
Column select
Memory Array
I/O Circuit
PVCC
PGND
3530B–STKD–2/4/05