K4H510438G SAMSUNG [Samsung semiconductor], K4H510438G Datasheet - Page 4
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K4H510438G
Manufacturer Part Number
K4H510438G
Description
512Mb G-die DDR SDRAM Specification
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.K4H510438G.pdf
(24 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
K4H510438G-HCCC
Manufacturer:
SAMSUNG
Quantity:
12 651
Company:
Part Number:
K4H510438G-HCCC
Manufacturer:
PHI
Quantity:
2 000
K4H510438G
K4H510838G
K4H511638G
1.0 Key Features
2.0 Ordering Information
3.0 Operating Frequencies
• V
• V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II
•
Note :
1. "L" of part number(12th digit) stands for RoHS compliant and Halogen-Free product.
2. "-B3"(DDR333, CL=2.5) can support "-B0"(DDR266, CL=2.5)
K4H510838G-LC/LCC
K4H511638G-LC/LCC
K4H510438G-LC/LB0
K4H510438G-LC/LB3
K4H510838G-LC/LB3
K4H511638G-LC/LB3
RoHS compliant
-. Read latency : DDR266(2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
DD
DD
: 2.5V ± 0.2V, V
: 2.6V ± 0.1V, V
Part No.
Speed @CL2.5
CL-tRCD-tRP
Speed @CL2
Speed @CL3
Lead-Free & Halogen-Free
DDQ
DDQ
128M x 4
32M x 16
64M x 8
: 2.5V ± 0.2V for DDR266, 333
: 2.6V ± 0.1V for DDR400
Org.
CC(DDR400@CL=3)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
166MHz
200MHz
3-3-3
Max Freq.
package
4 of 24
B3(DDR333@CL=2.5)
Interface
SSTL_2
SSTL_2
SSTL_2
133MHz
166MHz
2.5-3-3
-
Lead-Free & Halogen-Free
Lead-Free & Halogen-Free
Lead-Free & Halogen-Free
66pin TSOP II
66pin TSOP II
66pin TSOP II
Rev. 1.1 November 2009
Package
B0(DDR266@CL=2.5)
DDR SDRAM
100MHz
133MHz
2.5-3-3
-
Note
1, 2
1, 2
1, 2
1
1
1