SSD1820ATR1 ETC1 [List of Unclassifed Manufacturers], SSD1820ATR1 Datasheet - Page 15

• Manufacturer Part Number: SSD1820ATR1
• Description: LCD Segment / Common Driver with Controller CMOS
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

SOLOMON
LCD Driving Voltage Generator and Regulator
It takes a single supply input and generate necessary bias voltages.
It consists of:
1. 2X, 3X, 4X, 5X and 6X DC-DC voltage converter
2. Voltage Regulator
3. Bias Divider
command is enabled, this circuit block will divide the regulator output
(V
most of the display current comparing to traditional design.
between these voltage level pins (V
loading is heavy, capacitors and four additional resistors are suggest-
Oscillator Circuit
(Figure 7). The oscillator generates the clock for the DC-DC voltage
converter. This clock is also used in the Display Timing Generator.
L6
This module generates the LCD voltage needed for display output.
Please refer to application notes.
Please note that SSD1820A works up to 5X and SSD1820AT
works up to 4X only.
Feedback gain control for initial LCD voltage. External resistors
are connected between V
These resistors are chosen to give the desired VL6 according to
the following equation:
where V
) to give the LCD driving levels (V
If the output op-amp buffer option in Set Power Control Register
A low power consumption circuit design in this bias divider saves
Stablizing Capacitors (0.47~2uF) are required to be connected
This module is an On-Chip low power RC oscillator circuitry
known R
R
R
G = 1 if INTRS = VDD; REF = VDD
G = 0.84 if INTRS = VSS; REF = VDD
ref
1
2
V
V
V
V
is the software contrast level from 0 to 63.
is the resistance of the resistor between V
is the resistance of the resistors between V
is the internally generated reference voltage with a
L
L
con
con
6
6
1
and R
1 (
1 (
1 (
1 (
2
. Typical value for V
SS
R
R
R
R
63
63
and V
2
2
1
1
210
210
L2
)
)
- V
L2
R
, and between V
L5
- V
V
V
OSC1
) and V
L5
con
con
)
)
).
Internal pwell resistor
ref
V
V
SS
is 2.1V
G
G
ref
ref
. If the LCD panel
Oscillation Circuit
Figure 7. Oscillator Circuitry
SS
R
R
and V
and V
and VL6.
enable
R
L6
.
.
OSC2
ed to add to the application circuit as follows:
4. Contrast Control
5. Bias Ratio Selection circuitry
6. Self adjust temperature compensation circuitry
193/209 Bit Latch
plamode. Data will be fed to the HV-buffer Cell and level-shifted to the
required level.
Level Selector
voltage can be separated into two sets and used with different
cycles. Synchronization is important since it selects the required LCD
voltage level to the HV Buffer Cell, which in turn outputs the COM or
SEG LCD waveform.
V
A register carries the display signal information. In 128 X 65/81 dis-
Software control of 64 voltage levels of LCD voltage.
Software control of 1/ 4 to 1/10 bias ratio to match the characteris-
tic of LCD panel.
Note: SSD1820A has 1/4 to 1/9 bias only.
Provide 2 different compensation grade selections to satisfy the
various liquid crystal temperature grades. The grading can be
selected by software control. Defaulted temperature coefficient
(TC) value is -0.05% /
SSD1821 .
Level Selector is a control of the display synchronization. Display
SS
V
SS
Connections for heavy loading applications
Remarks: 1. C2 = 0.47 ~ 2.0uF
RL
enable
Buffer
V
L2
C2
Oscillator enable
SSD1820A/21 Series
RL
2. RL = 100K ~ 1M
o
C for SSD1820A and -0.07%/
V
L3
C2
(CL)
V
L4
C2
REV 1.4
RL
01/03
V
L5
C2
SSD1820A/21
RL
V
L6
o
C for
C2
15