M368L2923CUN-CLCC SAMSUNG [Samsung semiconductor], M368L2923CUN-CLCC Datasheet - Page 14
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M368L2923CUN-CLCC
Manufacturer Part Number
M368L2923CUN-CLCC
Description
DDR SDRAM Unbuffered Module
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.M368L2923CUN-CLCC.pdf
(25 pages)
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
AC Operating Conditions
Input/Output Capacitance
256MB, 512MB, 1GB Unbuffered DIMM
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0)
Input capacitance( CS0)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7, DM8(for ECC))
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0,CKE1)
Input capacitance( CS0, CS1)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7, DM8(for ECC))
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
2. The value of V
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Parameter/Condition
IX
Parameter
Parameter
is expected to equal 0.5*V
Output
Output Load Circuit (SSTL_2)
DDQ
Z0=50Ω
of the transmitting device and must track variations in the DC level of the same.
C
LOAD
Symbol
Symbol
Cout1
Cout2
Cout1
Cout2
CIN1
CIN2
CIN3
CIN4
CIN5
CIN1
CIN2
CIN3
CIN4
CIN5
=30pF
V
tt
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
=0.5*V
M368L3324CUS M368L6523CUS M381L6523CUM
Min
41
34
34
25
R
6
6
-
Min
M368L2923CUN
DDQ
65
42
42
28
10
10
T
-
=50Ω
0.5*VDDQ-0.2
VREF + 0.31
V
=0.5*V
REF
Max
45
38
38
30
7
7
-
Min
0.7
DDQ
Max
81
50
50
34
12
12
(VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)
-
Min
49
42
42
25
6
6
-
Rev. 1.0 February. 2005
0.5*VDDQ+0.2
VREF - 0.31
VDDQ+0.6
M381L2923CUM
Min
Max
69
44
44
28
10
10
10
Max
57
50
50
30
7
7
-
DDR SDRAM
Min
51
44
44
25
6
6
6
Max
87
53
53
34
12
12
12
Unit
V
V
V
V
Max
60
53
53
30
7
7
7
Unit
Note
pF
pF
pF
pF
pF
pF
pF
Unit
3
3
1
2
pF
pF
pF
pF
pF
pF
pF