M391B1G73BH0 SAMSUNG [Samsung semiconductor], M391B1G73BH0 Datasheet - Page 3

• Manufacturer Part Number: M391B1G73BH0
• Description: 240pin Unbuffered DIMM based on 4Gb B-die
• Manufacturer: SAMSUNG [Samsung semiconductor]

Unbuffered DIMM
Table Of Contents
240pin Unbuffered DIMM based on 4Gb B-die
1. DDR3 Unbuffered DIMM Ordering Information ............................................................................................................. 4
2. Key Features................................................................................................................................................................. 4
3. Address Configuration .................................................................................................................................................. 4
4. x64 DIMM Pin Configurations (Front side/Back side) ................................................................................................... 5
5. x72 DIMM Pin Configurations (Front side/Back side) ................................................................................................... 6
6. Pin Description ............................................................................................................................................................. 7
7. SPD and Thermal Sensor for ECC UDIMMs ................................................................................................................ 7
8. Input/Output Functional Description.............................................................................................................................. 8
9. Function Block Diagram: ............................................................................................................................................... 10
10. Absolute Maximum Ratings ........................................................................................................................................ 13
11. AC & DC Operating Conditions................................................................................................................................... 13
12. AC & DC Input Measurement Levels .......................................................................................................................... 14
13. AC & DC Output Measurement Levels ....................................................................................................................... 19
14. DIMM IDD specification definition ............................................................................................................................... 21
15. IDD SPEC Table ......................................................................................................................................................... 23
16. Input/Output Capacitance ........................................................................................................................................... 25
17. Electrical Characteristics and AC timing ..................................................................................................................... 26
18. Timing Parameters by Speed Grade .......................................................................................................................... 31
19. Physical Dimensions................................................................................................................................................... 39
8.1 Address Mirroring Feature ....................................................................................................................................... 9
9.1 4GB, 512Mx64 Non ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs) ..................................................... 10
9.2 8GB, 1Gx64 Non ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ....................................................... 11
9.3 8GB, 1Gx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ............................................................... 12
10.1 Absolute Maximum DC Ratings............................................................................................................................. 13
10.2 DRAM Component Operating Temperature Range .............................................................................................. 13
11.1 Recommended DC Operating Conditions (SSTL-15)............................................................................................ 13
12.1 AC & DC Logic Input Levels for Single-ended Signals .......................................................................................... 14
12.2 V
12.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 16
12.4 Slew Rate Definition for Single Ended Input Signals ............................................................................................. 18
12.5 Slew rate definition for Differential Input Signals ................................................................................................... 18
13.1 Single Ended AC and DC Output Levels ............................................................................................................... 19
13.2 Differential AC and DC Output Levels ................................................................................................................... 19
13.3 Single-ended Output Slew Rate ............................................................................................................................ 19
13.4 Differential Output Slew Rate ................................................................................................................................ 20
17.1 Refresh Parameters by Device Density................................................................................................................. 26
17.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 26
17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 26
18.1 Jitter Notes ............................................................................................................................................................ 37
18.2 Timing Parameter Notes........................................................................................................................................ 38
19.1 512Mbx8 based 512M x64 Module (1 Rank) - M378B5173BH0 ........................................................................... 39
19.2 512Mbx8 based 1Gx64/x72 Module (2 Ranks) - M378/91B1G73BH0 .................................................................. 40
8.1.1. DRAM Pin Wiring Mirroring .............................................................................................................................. 9
12.3.1. Differential Signals Definition ......................................................................................................................... 16
12.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. 16
12.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 17
12.3.4. Differential Input Cross Point Voltage ............................................................................................................ 18
17.3.1. Speed Bin Table Notes .................................................................................................................................. 30
REF
Tolerances.................................................................................................................................................... 15
datasheet
- 3 -
DDR3 SDRAM
Rev. 1.3