M378B2873GB0 SAMSUNG [Samsung semiconductor], M378B2873GB0 Datasheet - Page 22
M378B2873GB0
Manufacturer Part Number
M378B2873GB0
Description
240pin Unbuffered DIMM based on 1Gb G-die
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.M378B2873GB0.pdf
(41 pages)
Unbuffered DIMM
14. DIMM IDD specification definition
Symbol
IDD2P0
IDD2P1
IDD6ET
IDD4W
IDD2N
IDD2Q
IDD3N
IDD4R
IDD3P
IDD5B
IDD0
IDD1
IDD6
IDD7
IDD8
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
tern
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 8
and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
tern
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode
Registers
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode
Registers
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers
Signal: stable at 0
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8
Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers
at HIGH; Pattern Details: Refer to Component Datasheet for detail pattern
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 8
Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and
RTT: Enabled in Mode Registers
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8
Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
Self-Refresh Current: Extended Temperature Range (optional)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8
Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 8
between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and
the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:
Enabled in Mode Registers
RESET Low Current
RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :
FLOATING
2)
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
2)
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
datasheet
4)
4)
; Self-Refresh Temperature Range (SRT): Extended
; Self-Refresh Temperature Range (SRT): Normal
6)
1)
1)
3)
2)
2)
3)
; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
- 22 -
Description
2)
; ODT Signal: FLOATING
1)
1)
1)
1)
1)
1)
1)
1)
; AL: 0; CS: stable at 1; Command, Address, Bank
; AL: 0; CS: stable at 1; Command, Address, Bank
; AL: 0; CS: stable at 1; Command, Address, Bank
; AL: 0; CS: stable at 1; Command, Address, Bank
; AL: 0; CS: stable at 1; Command, Address, Bank
; AL: 0; CS: stable at 1; Command, Address, Bank
; AL: 0; CS: High between RD; Command, Address,
; AL: 0; CS: High between WR; Command, Address,
1)
; AL: 0; CS: High between REF; Command,
5)
; CKE: Low; External clock: Off; CK and CK:
5)
; CKE: Low; External clock: Off; CK and CK:
1)
; AL: 0; CS: High between ACT and PRE;
2)
; ODT Signal: FLOATING
1)
; AL: 0; CS: High between ACT, RD
DDR3 SDRAM
1)
2)
2)
; AL: CL-1; CS: High
; ODT Signal: stable
; ODT Signal: stable
Rev. 1.2
2)
; ODT
2)
2)
2)
;
;
;