HS9-80C85RH INTERSIL [Intersil Corporation], HS9-80C85RH Datasheet
HS9-80C85RH
Related parts for HS9-80C85RH
HS9-80C85RH Summary of contents
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February 1996 Features • Devices QML Qualified in Accordance With MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95824 and Intersil’ QM Plan • Radiation Hardened EPI-CMOS - Parametrics Guaranteed Transient Upset ...
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... Ordering Information PART NUMBER TEMPERATURE RANGE 5962R9582401QQC -55 5962R9582401QXC -55 5962R9582401VQC -55 5962R9582401VXC -55 HS1-80C85RH/SAMPLE HS9-80C85RH/SAMPLE Functional Diagram INTR INTERRUPT CONTROL ACCUMU- TEMP REG LATOR (8) (8) VDD POWER SUPPLY GND X1 CLK CONTROL GEN X2 READY CLK RD OUT HS-80C85RH SCREENING LEVEL +125 C MIL-PRF-38535 Level ...
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Pin Description PIN SYMBOL NUMBER TYPE A8 - A15 21-28 O Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address, 3-stated during Hold and Halt modes and during RESET. AD0-7 ...
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Pin Description (Continued) PIN SYMBOL NUMBER TYPE INTR 10 I INTA 11 O RST 5 RST 6.5 8 RST 7.5 7 TRAP 6 I RESET RESET OUT ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER A8-15 Valid Before Trailing Edge of ALE (Note 5) A0-7 Valid Before Trailing Edge of ALE READY Valid from Address Valid Address (A8-15) Valid After Control Width of Control Low (RD, WR, ...
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TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Input Capacitance CIN I/O Capacitance CI/O Output Capacitance COUT NOTE: 1. All measurements referenced to device ground. TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: The post irradiation test conditions and limits ...
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Waveforms X INPUT 1 CLK OUTPUT tXKR tXKF CLK A 8- tLL ALE tAL RD/INTA T1 CLK A ADDRESS 8-15 AD -AD ADDRESS 0 7 tLL ALE tAL WR tAC HS-80C85RH tCYC FIGURE ...
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Waveforms (Continued) T2 CLK HOLD tHDS HLDA BUS (ADDRESS, CONTROLS) T1 CLK tLCK A ADDRESS 8-15 AD -AD ADDRESS 0 7 tLA tLL ALE tAL tLC RD/INTA tLRY tAC tARY READY NOTE 1: READY MUST REMAIN STABLE DURING SETUP AND ...
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INSTRUCTION CODE MNEMONIC MOVE, LOAD, AND STORE MOVr1 MOV M MOV ...
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TABLE 9. INSTRUCTION SET SUMMARY (Continued) INSTRUCTION CODE MNEMONIC JPE JPO PCHL ...
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Functional Description The HS-80C85RH is a complete 8-bit parallel central pro- cessing unit implemented in a self aligned, silicon gate, CMOS technology. Its static design allows the device to be operated at any external clock frequency from a maximum of ...
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INSIDE THE EXTERNAL 80C85RH TRAP INTERRUPT REQUEST TRAP RESET IN SCHMITT RESET TRIGGER D VDD CLEAR TRAP F.F. INTERNAL TRAP ACKNOWLEDGE FIGURE 8. TRAP AND RESET IN CIRCUIT The TRAP interrupt is special in that is disables interrupts, but preserves ...
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HS-80C85RH Caveats 1. An important caveat that is applicable to CMOS devices in gen- eral is that unused inputs should never be left floating. This rule also applies to inputs connected to a tri- state bus. The need for external ...
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HS-80C85RH A8-15 AD0-7 ALE RD HS-80C85RH WR IO/M CLK RESET OUT READY TIMER OUT HS-81C56RH (RAM + I/O + COUNTER/TIMER) (6) (8) FIGURE 13. HS-80C85RH MINIMUM SYSTEM (MEMORY MAPPED I/ TRAP RST 7.5 RST 6.5 HS-80C85RH RST 5.5 ...
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Basic System Timing The HS-80C85RH has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8-bits of address on the Data Bus. Figure 15 shows an instruction fetch, memory read and I/O write cycle (as ...
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Metallization Topology DIE DIMENSIONS: 229 mils x 240 mils x 14 mils 1 mil METALLIZATION: Type: SiAl Å Å Thickness: 11k 2k GLASSIVATION: Type: SiO 2 Å Å Thickness Metallization Mask Layout TRAP (6) RST 7.5 (7) RST ...
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Packaging LEAD FINISH BASE METAL (b) SECTION A-A NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one ...
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All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, ...