GS82032A ETC1 [List of Unclassifed Manufacturers], GS82032A Datasheet - Page 3

• Manufacturer Part Number: GS82032A
• Description: 2M Synchronous Burst SRAM
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

TQFP Pin Description
E
Rev: 1.03 2/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
16, 38, 39, 42, 43, 66, 50, 51, 80, 1, 30
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
18, 19, 22, 23, 24, 25, 28, 29
4, 11, 20, 27, 54, 61, 70, 77
2, 3, 6, 7, 8, 9, 12, 13
Pin Location
46, 47, 48, 49
15, 41, 65, 91
37, 36
93, 94
95, 96
98, 92
84, 85
87
89
88
97
86
83
64
14
31
ADSP, ADSC
DQ
DQ
DQ
DQ
Symbol
B
B
A
E
A
C1
D1
V
A1
B1
ADV
LBO
GW
V
BW
C
V
NC
A
CK
0
1
E
ZZ
FT
2
G
DDQ
, A
, B
, B
, E
-DQ
-DQ
-DQ
-DQ
DD
SS
-
2
15
1
B
D
3
A8
B8
C8
D8
Type
3/23
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Address Strobe (Processor, Cache Controller). Active Low.
Byte Write Enable for DQ
Byte Write Enable for DQ
Address field LSB’s and Address Counter preset Inputs
Burst address counter advance enable. Active Low.
Global Write Enable. Writes all bytes. Active Low.
Byte Write. Writes all enabled bytes. Active Low.
Flow Through or Pipeline mode. Active Low.
Linear Burst Order mode. Active Low.
GS820E32T/Q-150/138/133/117/100/66
Sleep Mode control. Active High.
Clock Input Signal. Active High.
Data Input and Output pins.
Output driver power supply.
Output Enable. Active Low.
Chip Enable. Active High.
Chip Enable. Active Low.
I/O and Core Ground.
Core power supply.
Address Inputs
Description
No Connect
C
A
, DQ
, DQ
B
D
Data I/O’s. Active Low.
Data I/O’s. Active Low.
© 1999, Giga Semiconductor, Inc.
D