TSC695F ATMEL [ATMEL Corporation], TSC695F Datasheet
TSC695F
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TSC695F Summary of contents
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... KRADs (Si)) CMOS enhanced process (RTP). It has been specially designed for space has on-chip concurrent transient and permanent error detection. The TSC695F includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a Memory Controller and a DMA arbiter. For real-time applications, the TSC695F offers a high security watchdog, two timers, an interrupt controller, parallel and serial inter- faces ...
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... Block Diagram Figure 1. TSC695F Block Diagram 32-bit TAP Integer Clock Unit & Parity Reset Gen./Chk. Managt Error General Purpose Managt Timer General Purpose Interface GPI bits Pin Descriptions Table 1. Pin Descriptions Signal Type Active RA[31:0] I/O, RAPAR I/O RASI[3:0] I/O RSIZE[1:0] I/O RASPAR I/O CPAR I/O D[31:0] I/O CB[6:0] I/O DPAR ...
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... Factory test mode High Software debug mode Test (JTAG) clock Low Test (JTAG) reset Test (JTAG) mode select Test (JTAG) data input Test (JTAG) data output Main internal power Output driver power TSC695F Output buffer: 400 ...
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... A[31:0] IU Peripherals TSC695F TSC695F 4 The TSC695F used as an embedded processor requiring only memory and application specific peripherals to be added to form a complete on-board computer. All other system support functions are provided by the core. Glue Logic (BUFFEN, DDIR) (ROMCS, EXMCS, IOSEL[3:0], MEMWR, IOWR, OE, BUSRDY,...) ...
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... The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR is a 32-bit status and control register. It keeps track of rounding modes, floating-point trap types, queue status, condition codes, and various IEEE exception information. The floating-point queue contains the floating-point instruction currently under execution, along with its corresponding address. TSC695F 5 ...
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... Please refer to SPARC V7 Instruction-set Manual. Note: The execution of IFLUSH will cause an illegal instruction trap. The TSC695F is designed to allow easy interfacing to internal/external memory resources. Size (bytes) Data Size and Parity Options 128K → 16M ...
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... Exchange Memory read/write – Four individual I/O peripherals read/write A bus time-out function of 256 system clock cycles is provided for the bus ready con- trolled memory areas, i.e., the Extended PROM, Exchange Memory, Extended RAM, TSC695F Address MCNFR 0x 01F8 0010 IOCNFR 0x 01F8 0014 WSCNFR ...
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... This means that altogether 40 bits are used when the EDAC is enabled. The TSC695F EDAC uses a 7-bit Hamming code which detects any double bit error on the 40-bit bus as a non-correctable error. In addition, the EDAC detects all bits stuck-at- one and stuck-at-zero failure for any nibble in the data word as a non-correctable error ...
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... Retrying instruction but PC & nPC have to be re-adjusted 2.4 63h TSC695F enters (if not masked) in halt or reset mode Retrying instruction 2 2.5 61h TSC695F enters (if not masked) in halt or reset mode Parity error on control bus Parity error on data bus Parity error on address bus Access to protected or unimplemented area Uncorrectable error in memory Bus time out 3 ...
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... It is possible to mask each individual interrupt (except Watchdog time-out). The interrupts in the Interrupt Pending Register are cleared automatically when the interrupt is acknowledged. By programming the Interrupt Shape Register possible to define the external interrupts to either be active low or active high and to define the external interrupts to either be edge or level sensitive. TSC695F 10 Priority Trap Type (tt) Comments Idem “ ...
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... Simulta- neously, the timer starts counting a reset time-out period. If the timer is not acknowledged before the reset time-out period elapses, a reset is applied to TSC695F. Two full duplex asynchronous receiver transmitters (UART) are included. In software debug mode the UART’ ...
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... The SYSAV bit in the Error and Reset Status Register can be used by software to indi- cate system availability. The TSC695F includes a number of software test facilities such as EDAC test, Parity test, Interrupt test, Error test and a simple Test Access Port. These test functions are controlled using the Test Control Register. 4118H– ...
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... A variety of TSC695F test and diagnostic hardware functions, including boundary scan, internal scan, clock control and On-chip Debugger, are controlled through an IEEE 1149.1 (JTAG) standard Test Access Port (TAP). The TAP interfaces to the JTAG bus via 5 dedicated pins on the TSC695F chip. These pins are: • ...
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... Power Down Supply Current Icc PD for core processor TSC695F 14 Note: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... Description Input Capacitance Output Capacitance Input/Output Capacitance = 50 pF 2.5 V load ref Reference Edge – – – SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK- or SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK- SYSCLK+ SYSCLK+ SYSCLK- SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK- SYSCLK+ SYSCLK+ SYSCLK+ TSC695F Max ...
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... TSC695F 16 Max (ns) Comment – BUSRDY* setup time – BUSRDY* hold time IOSEL output delay 15 DMAAS setup time 20 1 formula of max DMAAS hold time 20 ...
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... Figure 3. 150 pF Buffer Response (Data from simulation) TSC695F 17 4118H–AERO–06/03 ...
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... Figure 4. 400 pF Buffer Response (Data from simulation) TSC695F 18 4118H–AERO–06/03 ...
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... Figure 5. OE*/400 pF Buffer Response (Data from simulation) 4118H–AERO–06/03 TSC695F 19 ...
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CLK2 SYSCLK t4_1 RA [31:0] FA1 t14 t14 ALE MEMCS* [0] MEMCS* [1] ROMCS* DDIR MEMWR* BUFFEN* t8 OE* D [31:0] FD1 DPAR FP1 CB [6:0] FC1 t60 ...
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SYSCLK t4_1 RA [31:0] FA1 ALE* t5 MEMCS* [0] t5 MEMCS* [1] DDIR MEMWR* BUFFEN* t8 OE* D [31:0] FD1 byte from RAM DPAR FP1 parity from RAM CB [6:0] FC1 checkbyte from RAM t60 INST MHOLD* ...
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SYSCLK t4_1 RA [31:0] FA1 LA1 ALE* t5 MEMCS* [0] t5 MEMCS* [1] DDIR MEMWR* BUFFEN [31:0] FD1 LD1 t9 DPAR FP1 LP1 t9 CB [6:0] FC1 ...
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SYSCLK ALE* t4_1 RA[31-0] FA1 t5 MEMCS*[0] t5 MEMCS*[1] DDIR MEMWR* IOWR* t8 OE* BUFFEN* t9 t10 D[31-0] FD1 CB[6-0] FC1 DPAR FP1 MHOLD* MEXC* MDS* t60 INST INULL 2 (RAM load correctable data) internal ...
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SYSCLK ALE* t4_1 RA[31-0] FA1 LD1 t5 MEMCS*[0] t5 MEMCS*[1] DDIR MEMWR* IOWR* t8 OE* BUFFEN* t9 D[31-0] FD1 CB[6-0] FC1 DPAR FP1 2-bit error on 40-bit data MHOLD* MEXC* MDS* t60 INST INULL 2 ...
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SYSCLK ALE* unimplemented address RA[31-0] FA1 LA1 t5 MEMCS*[0] MEMCS*[1] DDIR MEMWR* IOWR* BUFFEN* OE* t9 t10 D[31-0] FD1 MHOLD* MEXC* MDS* t60 INST INULL 3 (RAM fetch) 4 (null cycle) internal ...
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SYSCLK ALE* t4_1 t4_1 RA[31-0] FA1 t5 MEMCS*[0] IOSEL*[0] BUSRDY* t6 DDIR MEMWR* IOWR* t15 BUFFEN* t56 OE* t10 t61 t9 D[31-0] FD1 previous stored data t60 INST MHOLD* MDS* 2 (i/o store) (n-1) ...
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SYSCLK t14 ALE* t4_1 RA[31-0] FA1 t5 MEMCS*[0] IOSEL*[0] BUSRDY* DDIR MEMWR* IOWR* t15 BUFFEN* t56 t8 OE* t10 data driven by external buffers (c.f BUFFEN*) t9 D[31-0] FD1 t60 INST MHOLD* MDS* 2 ...
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SYSCLK ALE* t4_1 RA[31-0] FA1 t5 MEMCS*[0] t5 EXMCS* t6 DDIR MEMWR* IOWR* t15 BUFFEN* t56 OE* BUSRDY* t61 D[31-0] FD1 t60 INST MHOLD* MDS* 2 (xchgRAM store) rdy waiting rdy ...
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SYSCLK ALE* t4_1 RA[31-0] FA1 t5 MEMCS*[0] t5 EXMCS* DDIR MEMWR* IOWR* t15 BUFFEN* t56 OE* BUSRDY* D[31-0] FD1 t60 INST MHOLD* MDS* 2 (xchgRAM load) rdy waiting rdy waiting t2 ...
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SYSCLK t14 ALE* t4_1 RSIZE[0,1] t4_1 RA[31-0] FA1 BA[0, ROMCS* MEMCS*[0] DDIR MEMWR* t15 BUFFEN* t8 OE* D[31-8] D[7-0] t60 INST t16 t16 MHOLD* t17 MDS* 2 (8-bit ...
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ROM write) start of cycle SYSCLK ALE* t4_1 RA[31-0] FA1 SA1 BA[0,1] t4_1 RSIZE[0, MEMCS*[0] t5 ROMCS* t6 DDIR MEMWR* IOWR* t15 BUFFEN* t56 OE* t61 t9 D[31-0] FD1 t60 INST t16 MHOLD* ...
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... FZ2 FZ3 t30 early time for DMAREQ* desassertion t31 t29 t31 t31 t5 t5 t17 t17 t8 t56 t7 t6 t10 t10 t9 D SDn FD2 t10 t13 t13 t9 DSPn FP2 Parity generated by TSC695F if dpe =1, else, same timing as D[31-0] t10 t13 t13 t9 D SCn FC2 t16 ...
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SYSCLK RA[31:0] FA(-1) FA0 ALE* D[31:0] FD(-1) FD0 INULL t52 t53 EXTINT[i] EXTINTACK Sampled Sampled Prioritized Prioritized Latched Latched Taken Taken FA1 FA2 FA3 FA4 FD1 FD2 FD3 FD4 TTA0 TTA1 TSA0 TSA1 TSA2 TD0 TD1 TSD0 TSD1 t54 t54 ...
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SYSCLK RA[31:0] FAn-1 FAn RASI[3:0] 09H 09H RSIZE[1: ALE* SYSHALT* MHOLD* SYSAV CPUHALT* D[31:0] FDn-1 FDn FAn+1 09H 10 t14 t16 t49 t48 FAn+1 FAn+2 09H 09H 10 10 t14 t16 t49 t48 FDn+2 FDn+1 ...
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SYSCLK RA[31:0] FAn-1 RASI[3:0] 09H RSIZE[1:0] 10 ALE* t50 IUERR* SYSERR* MHOLD* SYSAV CPUHALT* D[31:0] FDn-1 FAn FAn+1 09H 09H 10 10 t14 t50 t49 t16 t49 t48 FDn ...
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SYSCLK SYSRESET* RA[31: RASI[3:0] RSIZE[1:0] t14 ALE* t46 INULL RESET* FA n+1 t48 t14 t47 t48 ...
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... Ta = Temperature of the surrounding ambient air (°C) R θ θ θ °C/W Figure 23. Thermal Model Cavity Package Table 8. Thermal Characteristics R θ - Value 0 0.4 R θ θ θ jc Die Conditions Unit Temperature °C/W 25/90°C TSC695F Heat Flow Air Blown air Stationary air 37 ...
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... MQFP-F Package TSC695F 38 4118H–AERO–06/03 ...
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... RA[21] 156 NOPAR VCCO 157 SYSHALT VSSO 158 CPUHALT RA[20] 159 VCCO RA[19] 160 VSSO RA[18] 161 SYSERR VCCO 162 SYSAV VSSO 163 EXTINT[4] TSC695F Pin Signal 193 DXFER 194 MEXC 195 VCCO 196 VSSO 197 RESET 198 SYSRESET 199 BA[1] 200 BA[0] 201 CB[6] 202 CB[5] 203 VCCO ...
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... TSC695F 40 Table 9. Pin Assignments (Continued) Pin Signal Pin 36 VCCO 100 37 VSSO 101 38 D[17] 102 39 D[16] 103 40 VCCI 104 41 VSSI 105 42 D[15] 106 43 D[14] 107 44 VCCO 108 45 VSSO 109 46 D[13] 110 47 D[12] 111 48 D[11] 112 49 D[10] 113 50 VCCO 114 51 VSSO 115 52 D[9] 116 53 D[8] 117 54 D[7] 118 55 D[6] 119 56 VCCO 120 57 VSSO 121 58 D[5] 122 ...
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... TSC695F Packaging Quality Flow MQFP-F256 Engineering Samples MQFP-F256 Standard Mil. MQFP-F256 QML-Q MQFP-F256 QML-V MQFP-F256 SCC B Die ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem ...