CYM1465ALPD-70I CYPRESS [Cypress Semiconductor], CYM1465ALPD-70I Datasheet

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CYM1465ALPD-70I

Manufacturer Part Number
CYM1465ALPD-70I
Description
512K x 8 PDIP Static RAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet

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CYM1465ALPD-70I
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Features
Functional Description
The CYM1465A is a high-performance CMOS static RAM or-
ganized as 512K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE), an active LOW
Output Enable (OE), and three-state drivers. This device has
Selection Guide
Cypress Semiconductor Corporation
Document #: 38-05269 Rev. **
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current ( A)
• 4.5V–5.5V operation
• CMOS SRAM for optimum speed and power
• Low active power (165 mW max.)
• Low standby power (L Version)—(110 W max)
• 2V data retention (L Version)
• JEDEC-compatible pinout
• 32-pin, 0.6-inch-wide DIP package
• TTL-compatible inputs and outputs
Logic Block Diagram
CE
WE
OE
A
A
A
A
A
A
A
A
A
A
0
1
4
5
6
7
12
14
16
17
INPUT BUFFER
512 x 256 x 8
ARRAY
DECODER
COLUMN
POWER
DOWN
3901 North First Street
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
an automatic power-down feature that reduces power con-
sumption by more than 99% when deselected.
Writing to the SRAM is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on the
eight input/output pins (I/O
written into the memory location specified on the address pins
(A
taking chip select (CE) and output enable (OE) LOW while
write enable (WE) remains inactive or HIGH. Under these con-
ditions, the contents of the memory location specified on the
address pins (A
priate data input/output pins (I/O
put/output pins (I/O0 through I/O7) are placed in a high imped-
ance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW).
The CYM1465A is available in a 32-pin 600-mil wide body
PDIP package.
0
through A
512K x 8 PDIP Static RAM
San Jose
CYM1465A-70
18
). Reading from the device is accomplished by
0
through A
70
20
20
Pin Configuration
0
18
GND
through I/O
I/O
I/O
I/O
CA 95134
A
A
A
A
) will appear on the eight appro-
A
A
A
A
A
A
A
A
18
16
14
12
7
6
5
4
3
2
1
0
0
1
2
0
through I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Revised March 15, 2002
S
Top View
7
) of the device is then
CYM1465A-85
DIP
CYM1465A
7
85
20
20
).The eight in-
408-943-2600
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
A
A
WE
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
CC
15
17
13
8
9
11
10
7
6
5
4
3

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CYM1465ALPD-70I Summary of contents

Page 1

Features • 4.5V–5.5V operation • CMOS SRAM for optimum speed and power • Low active power (165 mW max.) • Low standby power (L Version)—(110 W max) • 2V data retention (L Version) • JEDEC-compatible pinout • 32-pin, 0.6-inch-wide DIP ...

Page 2

Maximum Ratings (Above which the useful life may be impaired.) Storage Temperature ................................. – +150 C Ambient Temperature with Power Applied............................................... – +85 C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied ...

Page 3

Switching Characteristics Over the Operating Range Parameter READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW to Data Valid ACE t OE LOW to Data Valid ...

Page 4

Data Retention Waveform Switching Waveforms [6,7] Read Cycle No. 1 ADDRESS DATA OUT PREVIOUS DATA VALID [6,8] Read Cycle No HIGH IMPEDANCE DATA OUT t LZCS Notes HIGH for read cycle. ...

Page 5

Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) ADDRESS DATA IN DATA OUT DATA UNDEFINED Write Cycle No. 2 (CE Controlled) ADDRESS CE WE DATA IN DATA OUT DATA UNDEFINED Note goes ...

Page 6

... Ordering Information Speed (ns) Ordering Code 70 CYM1465ALPD-70C 70 CYM1465ALPD-70I 85 CYM1465ALPD-85C 85 CYM1465ALPD-85I Package Diagram Document #: 38-05269 Rev. ** © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Page 7

Revision History Document Title: CYM1465A 512K x 8 PDIP Static RAM Document Number: 38-05269 ISSUE REV. ECN NO. DATE ** 114171 3/19/02 Document #: 38-05269 Rev. ** ORIG. OF CHANGE DESCRIPTION OF CHANGE DSG Change from Spec number: 38-M-00036 to ...

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