ISL6722A INTERSIL [Intersil Corporation], ISL6722A Datasheet - Page 18

• Manufacturer Part Number: ISL6722A
• Description: Flexible Single Ended Current Mode PWM
• Manufacturer: INTERSIL [Intersil Corporation]

There is limited flexibility to adjust the current loop behavior
due to the need to provide overcurrent protection. Current
limit and the current loop gain are determined by the current
sense resistor and the ISET threshold. ISET was set at 1.0V,
near its maximum, to minimize noise effects. When
determining ISET, the internal gain and offset of the ISENSE
signal in the control IC must be taken into account. The
maximum peak primary current was determined earlier to be
1.87A, so a choice of 2.25A peak primary current for current
limit is reasonable. A current gain, A
selected to achieve this.
ISET
The control to output transfer function may be represented
as [2].
if we ignore the current feedback sampled-data effects:
The value of K may be determined by assuming all of the
output power is delivered by the 3.3V output at the threshold
of current limit. The maximum power allowed was
determined earlier as 15W, so:
I
v
where A
network, A
between the error amplifier and the PWM comparator.
The Type 2 compensation configuration has two poles and
one zero. The first pole is at the origin, and provides the
v
----- -
v
spk max
c max
o
c
(
=
(
R
C
K
ω
K
L
ω
V
R
=
)
o
s
z
o
c max
p
c
•
=
(
2.25 0.8 0.5
)
=
EXT
=
=
=
=
=
=
=
R
---------------------------------
I
------------------------- -
V
CS
spk max
V
SecondaryInduc
LoadResis
------------------- -
R
OutputCapaci
------------------- -
R
OutputCapaci
o
ISENSE
2
------------------------------------ -
c max
•
c
)
o
is the external gain of the current feedback
•
(
•
1
•
(
2
=
is the IC internal gain, and A
•
L
P
----------- - tsw
V
2
C
C
s
ControlVoltageRange
out
out
o
•
•
o
Tr
)
)
f
sw
•
•
A
+
tan
•
EXT
or
or
0.100
1
---------------- -
1
ce
+
+
tan
tan
=
•
------
ω
------ -
ω
s
s
tan
2
----------------------------------------- -
A
z
p
ce
ceE
18
CS
•
=
f
f
2.33
z
ce
p
------- - 5
3.3
15
1.00
=
•
SR
=
-------------------- -
A
•
×10
------------------------------------- -
2 π
-----------------------------
π R
COMP
EXT
•
•
1
×10
–
6
•
1
o
, of 0.5 V/A was
–
1
R
V
6
•
=
c
C
COMP
=
•
o
2.93
C
19.5
o
is the gain
ISL6722A, ISL6723A
(EQ. 39)
(EQ. 38)
V
A
integration characteristic which results in excellent DC
regulation. Referring to the “Typical Application - 48V Input
Dual Output Flyback, 3.3V @ 2.5A, 1.8V @ 1.0A” on page 4,
the remaining pole and zero for the compensator are located
at:
f
f
The ratio of R
determine the mid band gain of the error amplifier.
A
From Equation 27, it can be seen that the control to output
transfer function frequency dependence is a function of the
output load resistance, the value of output capacitance, and
the output capacitance ESR. These variations must be
considered when compensating the control loop. The worst
case small signal operating point for the converter is at
minimum Vin, maximum load, maximum C
minimum ESR.
The higher the desired bandwidth of the converter, the more
difficult it is to create a solution that is stable over the entire
operating range. A good rule of thumb is to limit the
bandwidth to about f
will be further limited due to the low GBWP of the
LM431-based Error Amplifier and the opto-coupler. A
bandwidth of approximately 5kHz was selected.
For the EA compensation, the first pole is placed at the
origin by default (C
zero is placed below the crossover frequency, f
around 1/3 f
ESR zero or at one half of the switching frequency. The
midband gain is then adjusted to obtain the desired
crossover frequency. If the phase margin is not adequate,
the crossover frequency may have to be reduced.
Using this technique to determine the compensation, the
following values for the EA components were selected.
R
R
C
C
pc
zc
midband
17
20
13
14
=
=
= R
= open
= 100nF
= 100pF
------------------------------------------------------------
2 π R
------------------------------------------- -
2 π R
•
•
18
=
•
•
= R
C
co
R
----------------------------------------------- -
1
13
15
15
15
15
. The second pole is placed at the lower of the
15
+
•
R
•
•
to the parallel combination of R
C
C
C
17
= 1kΩ
(
R
14
13
14
14
•
17
sw
R
•
is an integrating capacitor). The first
+
C
18
/4. For this example, the bandwidth
R
13
18
≈
)
------------------------------------------- -
2 π R
•
•
1
15
•
C
14
OUT
, and
co
17
, usually
and R
July 11, 2007
(EQ. 40)
(EQ. 41)
(EQ. 42)
FN9237.1
18