EDD1216AATA-5 ELPIDA [Elpida Memory], EDD1216AATA-5 Datasheet - Page 36

• Manufacturer Part Number: EDD1216AATA-5
• Description: 128M bits DDR SDRAM (8M words x 16 bits, DDR400)
• Manufacturer: ELPIDA [Elpida Memory]

A Write command to the consecutive Precharge command interval (same bank)
The minimum interval tWPD is necessary between the write command and the precharge command.
Precharge Termination in Write Cycles
During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command
of the same bank. In order to write the last input data, tWR (min) must be satisfied. When the precharge command
is issued, the invalid data must be masked by DM.
Data Sheet E0443E40 (Ver. 4.0)
Command
Command
DQS
DQS
/CK
/CK
DM
DM
DQ
DQ
CK
CK
WRIT
WRIT
t0
t0
WRITE to PRECHARGE Command Interval (same bank) (BL = 4)
Precharge Termination in Write Cycles (same bank) (BL = 4)
in0
in0
t1
t1
in1
in1
Data masked
Last data input
in2
in2
t2
t2
in3
in3
NOP
tWPD
NOP
t3
t3
36
tWR
t4
t4
tWR
PRE/PALL
t5
t5
EDD1216AATA-5
PRE/PALL
t6
t6
NOP
t7
t7
NOP