HCTS374DMSR INTERSIL [Intersil Corporation], HCTS374DMSR Datasheet
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HCTS374DMSR
Related parts for HCTS374DMSR
HCTS374DMSR Summary of contents
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... CMOS/SOS Logic Family. The HCTS374MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE HCTS374DMSR HCTS374KMSR HCTS374D/Sample HCTS374K/Sample HCTS374HMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. ...
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Functional Diagram ( 13, 14, 17, 18) D COMMON CONTROLS =High Level (Steady State) L =Low Level (Steady State) X =Immaterial Z =High Impedance ...
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Absolute Maximum Ratings Supply Voltage (VCC -0.5V to +7.0V Input Voltage Range, All Inputs . . ...
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TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Clock to Q TPLH VCC = 4.5V TPHL VCC = 4.5V Enable to Output TPZL VCC = 4.5V TPZH VCC = 4.5V Disable to Output TPLZ, VCC = 4.5V TPHZ NOTES: 1. ...
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TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V Output Current IOH VCC ...
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CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. Alternate Group A testing in ...
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Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...
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AC Timing Diagrams tr tf INPUT LEVEL 90 10% 10% TW TPLH VS Qn FIGURE 1. CLOCK TO OUTPUT DELAYS AND CLOCK PULSE WIDTH TTLH VOH 80% 20% OUTPUT VOL FIGURE 3. OUTPUT TRANSITION TIME AC Load ...
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Three-State Low Timing Diagrams VIH INPUT VS VIL TPZL VOZ VT OUTPUT VOL THREE-STATE LOW VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VT 1.30 VW 0.90 VIL 0 GND 0 Three-State High Timing Diagrams VIH INPUT VS ...
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Die Characteristics DIE DIMENSIONS: 108 x 106 mils METALLIZATION: Type: AlSi Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY 2 A/cm BOND PAD SIZE: 100 ...
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All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, ...