HCTS574HMSR INTERSIL [Intersil Corporation], HCTS574HMSR Datasheet
HCTS574HMSR
Related parts for HCTS574HMSR
HCTS574HMSR Summary of contents
Page 1
... SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE HCTS574DMSR HCTS574KMSR HCTS574D/Sample HCTS574K/Sample HCTS574HMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HCTS574MS Radiation Hardened Octal D-Type Flip-Flop, Three-State, Positive Edge Triggered Pinouts 2 ...
Page 2
Functional Diagram D COMMON CONTROLS High Level Low Level Immaterial High Impedance = Transition from Low to High Level Q0 = The level of ...
Page 3
Absolute Maximum Ratings Supply Voltage (VCC -0.5V to +7.0V Input Voltage Range, All Inputs . . ...
Page 4
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Clock to Q TPLH, VCC = 4.5V TPHL Enable to Ouptput TPZL VCC = 4.5V TPZH VCC = 4.5V Disable to Output TPLZ, VCC = 4.5V TPHZ NOTES: 1. All voltages referenced ...
Page 5
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V Output Current IOH VCC ...
Page 6
CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTE: 1. Alternate Group A testing in ...
Page 7
Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...
Page 8
AC Timing Diagrams TR TF INPUT LEVEL 90 10% 10% TW TPLH VS FIGURE 1. CLOCK TO OUTPUT DELAYS AND CLOCK PULSE WIDTH TTLH VOH 80% 20% OUTPUT VOL FIGURE 3. OUTPUT TRANSITION TIME AC Load Circuit ...
Page 9
Three-State Low Timing Diagrams VIH INPUT VS VIL TPZL VOZ VT OUTPUT VOL THREE-STATE LOW VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VT 1.30 VW 0.90 GND 0 Three-State High Timing Diagrams VIH INPUT VS VIL TPZH ...
Page 10
Die Characteristics DIE DIMENSIONS: 101 x 85 mils METALLIZATION: Type: SiAl Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND PAD SIZE: 100 ...
Page 11
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, ...