EM636165TS7 Etron Technology Inc., EM636165TS7 Datasheet

EM636165TS7

Manufacturer Part Number

EM636165TS7

Description

TSOP50

Manufacturer

Etron Technology Inc.

Datasheet

1.EM636165TS7.pdf (73 pages)

Specifications of EM636165TS7

Date_code

04+

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

EM636165TS7

Manufacturer:

ETRON

Quantity:

20 000

Current page: 1 of 73
Download datasheet (2Mb)

Features

Ordering Information

1. Operating temperature : 0~70 C

2. Industrial Operating temperature : -40~85 C

Etron Technology, Inc.

No. 6, Technology Road V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C

TEL: (886)-3-5782345

Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.

CK3

RAS

AC3

Key Specifications

EM636165TS-5

EM636165TS-55

EM636165TS-6

EM636165TS-7

EM636165TS-8

EM636165TS-10

EM636165TS-10 I

Fast access time: 4.5/5/5/5.5/6.5/7.5 ns

Fast clock rate: 200/183/166/143/125/100 MHz

Fully synchronous operation

Internal pipelined architecture

512K word x 16-bit x 2-bank

Programmable Mode registers

- CAS# Latency: 1, 2, or 3

- Burst Length: 1, 2, 4, 8, or full page

- Burst Type: interleaved or linear burst

- Burst stop function

Individual byte controlled by LDQM and UDQM

Auto Refresh and Self Refresh

4096 refresh cycles/64ms

CKE power down mode

Single +3.3V 0.3V power supply

Interface: LVTTL

50-pin 400 mil plastic TSOP II package

Part Number

Clock Cycle time(min.)

Row Active time(max.)

Access time from CLK(max.)

Row Cycle time(min.)

EM636165

Frequency

200MHz

183MHz

166MHz

143MHz

125MHz

100MHz

FAX: (886)-3-5778671

30/32/36/42/48/60 ns

4.5/5/5/5.5/6.5/7.5 ns

48/48/54/63/72/90 ns

-5/55/6/7/8/10

1Mega x 16 Synchronous DRAM (SDRAM)

5/5.5/6/7/8/10ns

Package

TSOP II

Overview

synchronous DRAM containing 16 Mbits. It is internally

configured as a dual 512K word x 16 DRAM with a

synchronous interface (all signals are registered on the

positive edge of the clock signal, CLK). Each of the

512K x 32 bit banks is organized as 2048 rows by 256

columns by 16 bits. Read and write accesses to the

SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of

locations in a programmed sequence. Accesses begin

with the registration of a BankActivate command which

is then followed by a Read or Write command.

or Write burst lengths of 1, 2, 4, 8, or full page, with a

burst termination option. An auto precharge function

may be enabled to provide a self-timed row precharge

that is initiated at the end of the burst sequence. The

refresh functions, either Auto or Self Refresh are easy

to use. By having a programmable mode register, the

system can choose the most suitable modes to

maximize its performance. These devices are well

suited

bandwidth

performance PC applications.

The EM636165 SDRAM is a high-speed CMOS

The EM636165 provides for programmable Read

for

Pin Assignment (Top View)

LDQM

CAS#

RAS#

WE#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS#

A11

A10

and

SSQ

DDQ

SSQ

DDQ

applications

particularly

Preliminary (Rev. 1.2, 10/99)

requiring

well

EM636165

suited

high

Vss

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

UDQM

CLK

CKE

Vss

SSQ

DDQ

SSQ

DDQ

memory

high

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