QL4009-1PF100I QuickLogic Corp, QL4009-1PF100I Datasheet
QL4009-1PF100I
Manufacturer Part Number
QL4009-1PF100I
Description
Manufacturer
QuickLogic Corp
Datasheet
1.QL4058-0PQ240M.pdf
(45 pages)
Specifications of QL4009-1PF100I
Package
QFP
Date_code
09+
Device Highlights
High Performance & High Density
• Up to 90,000 usable PLD gates with up to
• 300 MHz 16-bit counters, 400 MHz datapaths,
• 0.35 µm four-layer metal non-volatile CMOS
High Speed Embedded SRAM
• Up to 22 dual-port RAM modules, organized in
• 5 ns access times, each port independently
• Fast and efficient for FIFO, RAM, and ROM
Easy to Use/Fast Development
Cycles
• 100% routable with 100% utilization and
• Variable-grain logic cells provide high
• Comprehensive design tools include high quality
Advanced I/O Capabilities
• Interfaces with 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V busses for
• Full JTAG boundary scan
• I/O cells with individually controlled registered
© 2007 QuickLogic Corporation
316 I/Os
160+ MHz FIFOs
process
user-configurable 1,152 bit blocks
accessible
functions
complete pin-out stability
performance and 100% utilization
Verilog/VHDL synthesis
-1/-2/-3/-4 speed grades
input path and output enables
QuickRAM Family Data Sheet
• • • • • •
QuickRAM ESP Combining Performance, Density and
Embedded RAM
Up to 316 I/O Pins
• Up to 308 bi-directional input/output pins,
• Eight high-drive input/distributed network pins
Eight Low-Skew Distributed
Networks
• Two array clock/control networks are available to
• Six global clock/control networks available to the
High Performance Silicon
• Input + logic cell + output total delays under 6 ns
• Data path speeds over 400 MHz
• Counter speeds over 300 MHz
• FIFO speeds over 160+ MHz
Blocks
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
the logic cell flip-flop; clock, set, and reset inputs
— each can be driven by an input-only pin
logic cell; F1, clock, set, and reset inputs and the
data input, I/O register clock, reset, and enable
inputs as well as the output enable control—each
can be driven by an input-only, I/O pin, any logic
cell output, or I/O cell feedback
RAM
22
Figure 1: QuickRAM Block Diagram
www.quicklogic.com
Hi gh Speed
Logic Cells
Interface
1,584
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