W27E257-15 WINBOND [Winbond], W27E257-15 Datasheet - Page 2

• Manufacturer Part Number: W27E257-15
• Description: 32K X 8 ELECTRICALLY ERASABLE EPROM
• Manufacturer: WINBOND [Winbond]

FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27E257 has two control functions, both of which produce data
at the outputs.
When addresses are stable, the address access time (T
(T
are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E257 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when V
lower than V
address pins equal V
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if V
V
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when V
(12V), V
equal the desired inputs. Pulsing CE low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether or not they have been successfully
programmed with the desired data. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
program margin. This mode will be entered after the program operation if V
and OE = V
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE = V
CE is for power control and chip select. OE controls the output buffer to gate data to the output pins.
CE and OE pins, the W27E257 may have common inputs.
IL
CE
.
), and data are available at the outputs T
CC
= V
IL
CC
.
CP
), A9 = V
(5V), OE = V
IH
IL
, erasing or programming of non-target chips is inhibited, so that except for the
and data input pins equal V
HH
(14V), A0 = V
PP
IH
is raised to V
, the address pins equal the desired address, and the input pins
IL
OE
PE
(0.8V or below but higher than GND), and all other
- 2 -
after the falling edge of OE, if T
(14V), V
IH
. Pulsing CE low starts the erase operation.
ACC
CC
) is equal to the delay from CE to output
= V
PP
CE
= V
(5V), OE = V
PE
(14V), CE = V
PP
= V
ACC
PP
PP
IH
(2V or above but
W27E257
(12V), CE = V
is raised to V
and T
IH
, and OE =
CE
timings
IH
PP
,